M1AFS600-2PQ256ES datasheet, PDF

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M1AFS600-2PQ256ES: DescriptionFPGA, 600000 GATES, PBGA256; Categorysemiconductor Programmable logic devices; File Size10MB，318 Pages; ManufacturerActel; Websitehttp://www.actel.com/

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M1AFS600-2PQ256ES Overview

FPGA, 600000 GATES, PBGA256

M1AFS600-2PQ256ES Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	256
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	1.58 V
Minimum supply/operating voltage	1.42 V
Rated supply voltage	1.5 V
Processing package description	1 MM PITCH, GREEN, FBGA-256
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID array, low PROFILE
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	tin silver copper
Terminal location	BOTTOM
Packaging Materials	Plastic/Epoxy
Temperature level	INDUSTRIAL
organize	600000 doors
Programmable logic type	FIELD PROGRAMMABLE GATE array
Number of equivalent gate circuits	600000

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Preliminary v1.7

Actel Fusion Mixed-Signal FPGAs

Family with Optional ARM

Support

Features and Benefits

High-Performance Reprogrammable Flash

Technology

•

Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process

Nonvolatile, Retains Program when Powered Off

Live at Power-Up (LAPU) Single-Chip Solution

350 MHz System Performance

– Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz

Low Power Consumption

• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

• Sleep and Standby Low Power Modes

In-System Programming (ISP) and Security

• Secure ISP with 128-Bit AES via JTAG

• FlashLock

to Secure FPGA Contents

Embedded Flash Memory

• User Flash Memory – 2 Mbits to 8 Mbits

– Configurable 8-, 16-, or 32-Bit Datapath

– 10 ns Access in Read-Ahead Mode

• 1 kbit of Additional FlashROM

Advanced Digital I/O

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages – Up to 5 Banks per Chip

• Single-Ended

I/O

Standards:

LVTTL,

LVCMOS

3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and

LVCMOS 2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS

– Built-In I/O Registers

– 700 Mbps DDR Operation

• Hot-Swappable I/Os

• Programmable Output Slew Rate, Drive Strength, and Weak

Pull-Up/Down Resistor

• Pin-Compatible Packages across the Fusion Family

Integrated A/D Converter (ADC) and Analog I/O

•

Up to 12-Bit Resolution and up to 600 ksps

Internal 2.56 V or External Reference Voltage

ADC: Up to 30 Scalable Analog Input Channels

High-Voltage Input Tolerance: –10.5 V to +12 V

Current Monitor and Temperature Monitor Blocks

Up to 10 MOSFET Gate Driver Outputs

– P- and N-Channel Power MOSFET Support

– Programmable 1, 3, 10, 30 µA and 20 mA Drive Strengths

• ADC Accuracy is Better than 1%

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

• True Dual-Port SRAM (except ×18)

• Programmable Embedded FIFO Control Logic

On-Chip Clocking Support

•

Internal 100 MHz RC Oscillator (accurate to 1%)

Crystal Oscillator Support (32 kHz to 20 MHz)

Programmable Real-Time Counter (RTC)

6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated

PLLs

– Phase Shift, Multiply/Divide, and Delay Capabilities

Soft ARM7™ Core Support in M7 and M1 Fusion Devices

• ARM Cortex™-M1 (without debug), CoreMP7Sd (with

debug) and CoreMP7S (without debug)

Fusion Family

Fusion Devices

ARM-Enabled

Fusion Devices

CoreMP7

Cortex-M1

AFS090

AFS250

M1AFS250

AFS600

M7AFS600

M1AFS600

600,000

13,824

Yes

108

172

AFS1500

M1AFS1500

1,500,000

38,400

Yes

270

252

System Gates

Tiles (D-flip-flops)

Secure (AES) ISP

General

Information

PLLs

Globals

Flash Memory Blocks (2 Mbits)

Total Flash Memory Bits

Memory

FlashROM Bits

RAM Blocks (4,608 bits)

RAM kbits

Analog Quads

Analog Input Channels

Analog and I/Os

Gate Driver Outputs

I/O Banks (+ JTAG)

Maximum Digital I/Os

Analog I/Os

90,000

2,304

Yes

250,000

6,144

Yes

114

Notes:

1. Refer to the

CoreMP7

datasheet for more information.

2. Refer to the

Cortex-M1

product brief for more information.

October 2008

1 – Fusion Device Family Overview

Introduction

The Actel Fusion

mixed-signal FPGA satisfies the demand from system architects for a device that

simplifies design and unleashes their creativity. As the world’s first mixed-signal programmable

logic family, Fusion integrates mixed-signal analog, flash memory, and FPGA fabric in a monolithic

device. Actel Fusion devices enable designers to quickly move from concept to completed design

and then deliver feature-rich systems to market. This new technology takes advantage of the

unique properties of Actel flash-based FPGAs, including a high-isolation, triple-well process and the

ability to support high-voltage transistors to meet the demanding requirements of mixed-signal

system design.

Actel Fusion mixed-signal FPGAs bring the benefits of programmable logic to many application

areas, including power management, smart battery charging, clock generation and management,

and motor control. Until now, these applications have only been implemented with costly and

space-consuming discrete analog components or mixed-signal ASIC solutions. Actel Fusion mixed-

signal FPGAs present new capabilities for system development by allowing designers to integrate a

wide range of functionality into a single device, while at the same time offering the flexibility of

upgrades late in the manufacturing process or after the device is in the field. Actel Fusion devices

provide an excellent alternative to costly and time-consuming mixed-signal ASIC designs. In

addition, when used in conjunction with the Actel or ARM-based soft MCU core, Actel Fusion

technology represents the definitive mixed-signal FPGA platform.

Flash-based Fusion devices are live at power-up. As soon as system power is applied and within

normal operating specifications, Fusion devices are working. Fusion devices have a 128-bit flash-

based lock and industry-leading AES decryption, used to secure programmed intellectual property

(IP) and configuration data. Actel Fusion devices are the most comprehensive single-chip analog

and digital programmable logic solution available today.

To support this new ground-breaking technology, Actel has developed a series of major tool

innovations to help maximize designer productivity. Implemented as extensions to the popular

Actel Libero

Integrated Design Environment (IDE), these new tools allow designers to easily

instantiate and configure peripherals within a design, establish links between peripherals, create

or import building blocks or reference designs, and perform hardware verification. This tool suite

will also add comprehensive hardware/software debug capability as well as a suite of utilities to

simplify development of embedded soft-processor-based solutions.

General Description

The Actel Fusion family, based on the highly successful ProASIC

3 and ProASIC3E Flash FPGA

architecture, has been designed as a high-performance, programmable, mixed-signal platform. By

combining an advanced flash FPGA core with flash memory blocks and analog peripherals, Fusion

devices dramatically simplify system design and, as a result, dramatically reduce overall system cost

and board space.

The state-of-the-art flash memory technology offers high-density integrated flash memory blocks,

enabling savings in cost, power, and board area relative to external flash solutions, while providing

increased flexibility and performance. The flash memory blocks and integrated analog peripherals

enable true mixed-mode programmable logic designs. Two examples are using an on-chip soft

processor to implement a fully functional Flash MCU and using high-speed FPGA logic to offer

system and power supervisory capabilities. Live at power-up and capable of operating from a single

3.3 V supply, the Fusion family is ideally suited for system management and control applications.

The devices in the Fusion family are categorized by FPGA core density. Each family member

contains many peripherals, including flash memory blocks, an analog-to-digital-converter (ADC),

high-drive outputs, both RC and crystal oscillators, and a real-time counter (RTC). This provides the

Pr e li m i n a ry v1 . 7

1-1

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