IDT72V3680L39268BBGI datasheet, PDF

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IDT72V3680L39268BBGI: DescriptionFIFO, 16KX36, 5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-144; Categorystorage storage; File Size454KB，46 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT72V3680L39268BBGI Overview

FIFO, 16KX36, 5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-144

IDT72V3680L39268BBGI Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	13 X 13 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-144
Contacts	144
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	5 ns
period time	7.5 ns
JESD-30 code	S-PBGA-B144
JESD-609 code	e1
length	13 mm
memory density	589824 bit
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	144
word count	16384 words
character code	16000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	16KX36
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.97 mm
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	13 mm
Base Number Matches	1

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3.3V HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO

1,024 x 36, 2,048 x 36

4,096 x 36, 8,192 x 36

16,384 x 36, 32,768 x 36

IDT72V3640, IDT72V3650

IDT72V3660, IDT72V3670

IDT72V3680, IDT72V3690

Zero latency retransmit

Auto power down minimizes standby power consumption

Master Reset clears entire FIFO

Partial Reset clears data, but retains programmable settings

Empty, Full and Half-Full flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of eight preselected offsets

Selectable synchronous/asynchronous timing modes for Almost-

Empty and Almost-Full flags

Program programmable flags by either serial or parallel means

Select IDT Standard timing (using

and

flags) or First Word

Fall Through timing (using

and

flags)

Output enable puts data outputs into high impedance state

Easily expandable in depth and width

JTAG port, provided for Boundary Scan function (PBGA Only)

Independent Read and Write Clocks (permit reading and writing

simultaneously)

Available in a 128-pin Thin Quad Flat Pack (TQFP) or a 144-pin Plastic

Ball Grid Array (PBGA) (with additional features)

High-performance submicron CMOS technology

Industrial temperature range (–40°C to +85°C) is available

Green parts available, see ordering information

FEATURES:

•

Choose among the following memory organizations:

Commercial

IDT72V3640



1,024 x 36

IDT72V3650



2,048 x 36

IDT72V3660



4,096 x 36

IDT72V3670



8,192 x 36

IDT72V3680



16,384 x 36

IDT72V3690



32,768 x 36

Up to 166 MHz Operation of the Clocks

User selectable Asynchronous read and/or write ports (PBGA Only)

User selectable input and output port bus-sizing

- x36 in to x36 out

- x36 in to x18 out

- x36 in to x9 out

- x18 in to x36 out

- x9 in to x36 out

Pin to Pin compatible to the higher density of IDT72V36100 and

IDT72V36110

Big-Endian/Little-Endian user selectable byte representation

5V input tolerant

Fixed, low first word latency

•

FUNCTIONAL BLOCK DIAGRAM

*Available on the PBGA package only.

-D

(x36, x18 or x9)

WEN

WCLK/WR

INPUT REGISTER

LD SEN

OFFSET REGISTER

FF/IR

PAF

EF/OR

PAE

FWFT/SI

PFM

FSEL0

FSEL1

ASYW

WRITE CONTROL

LOGIC

RAM ARRAY

1,024 x 36, 2,048 x 36

4,096 x 36, 8,192 x 36

16,384 x 36, 32,768 x 36

FLAG

LOGIC

WRITE POINTER

READ POINTER

MRS

PRS

TCK

TRST

TMS

TDI

TDO

CONTROL

LOGIC

BUS

CONFIGURATION

RESET

LOGIC

OUTPUT REGISTER

READ

CONTROL

LOGIC

ASYR

RCLK/RD

JTAG CONTROL

(BOUNDARY SCAN)

-Q

(x36, x18 or x9)

REN

4667 drw01

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES



NOVEMBER 2005

DSC-4667/14

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