M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
RENESAS MCU
REJ03B0127-0151
Rev.1.51
Jul 31, 2008
1.
1.1
Overview
Features
The M32C/87 Group (M32C/87, M32C/87A, M32C/87B) is a single-chip control MCU, fabricated using high-
performance silicon gate CMOS technology, embedding the M32C/80 Series CPU core. The M32C/87 Group (M32C/
87, M32C/87A, M32C/87B) is housed in 144-pin and 100-pin plastic molded LQFP/QFP packages.
With a 16-Mbyte address space, this MCU combines advanced instruction manipulation capabilities to process
complex instructions by less bytes and execute instructions at higher speed.
The M32C/87 Group (M32C/87, M32C/87A, M32C/87B) has a multiplier and DMAC adequate for office automation,
communication devices and industrial equipment, and other high-speed processing applications.
1.1.1
Applications
Audio components, cameras, office equipment, communication devices, mobile devices, etc.
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
1. Overview
1.1.2
Table 1.1
Item
CPU
Specifications
Specifications (144-Pin Package) (1/2)
Function
Central processing
unit
Specification
M32C/80 core (multiplier: 16 bits × 16 bits
→
32 bits
multiply-addition operation instructions: 16 × 16 + 48
→
48 bits)
• Basic instructions: 108
• Minimum instruction execution time:
31.3 ns (f(CPU) = 32 MHz, VCC1 = 4.2 to 5.5 V)
41.7 ns (f(CPU) = 24 MHz, VCC1 = 3.0 to 5.5 V)
• Operating modes: Single-chip mode, memory expansion mode,
and microprocessor mode
See
Tables 1.5 to 1.7 Product List.
Vdet3 detection function, Vdet4 detection function,
cold start/warm start determination function
• Address space: 16 Mbytes
• External bus interface: 1 to 7 wait states can be inserted,
4 chip select outputs, 3 V and 5 V interfaces
• Bus format: Switchable between separate bus and multiplexed
bus formats, switchable data bus width (8-bit or 16-bit)
• 4 circuits:
Main clock, sub clock, on-chip oscillator,
PLL frequency synthesizer
• Oscillation stop detection:
Main clock oscillation stop detection function
• Frequency divider circuit:
Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16
• Low power consumption features: Wait mode, stop mode
• Interrupt vectors: 70
• External interrupt inputs: 14 (NMI, INT × 9, key input × 4)
• Interrupt priority levels: 7
15-bit × 1 channel (with prescaler)
• 4 channels, cycle steal method
• Trigger sources: 43
• Transfer modes: 2 (single transfer and repeat transfer)
• Can be activated by all peripheral function interrupt sources
• Transfer modes: 2 (single transfer and burst transfer)
• Immediate transfer, calculation transfer, and chain transfer
functions
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode,
pulse width modulation (PWM) mode,
Event counter 2-phase pulse signal processing (2-phase
encoder input) × 3
16-bit timer × 6
Timer mode, event counter mode, pulse period measurement
mode, pulse width measurement mode
3-phase inverter control × 1 (using timer A1, timer A2, timer A4,
and timer B2)
On-chip dead time timer
Tables 1.1 to 1.4 list the specifications of the M32C/87 Group (M32C/87, M32C/87A, M32C/87B).
Memory
ROM, RAM, data
flash
Power Supply Voltage Detection
External Bus
Expansion
Bus/memory
expansion function
Clock
Clock generation
circuits
Interrupts
Watchdog Timer
DMA
DMAC
DMACII
Timer
Timer A
Timer B
Timer function for
3-phase motor
control
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 1.2
Specifications (144-Pin Package) (2/2)
1. Overview
Item
Function
Serial Interface UART0 to UART4
UART5, UART6
A/D Converter
CRC-CCITT (X
16
+ X
12
+ X
5
+ 1) compliant
X/Y Converter
16 bits x 16 bits
Intelligent I/O
16-bit timer × 2
• Time measurement function (input capture): 8 channels
• Waveform generation function (output compare): 16 channels
• Communication function: Clock synchronous mode, clock
asynchronous mode, HDLC data processing mode,
IEBus (optional)
(1)(3)
• 2-phase pulse signal processing (2-phase encoder input) × 1
ROM Correction Function
Address match interrupt × 8
CAN modules
Supporting CAN 2.0B specification
M32C/87: 16 slots × 2 channels, M32C/87A: 16 slots × 1 channel
M32C/87B: none
I/O Ports
Programmable I/O
• Input only: 1
ports
• CMOS I/O: 121 with selectable pull-up resistor
• N channel open drain ports: 2
Flash Memory
• Erase and program voltage:
3.3 V ± 0.3 V or 5.0 V ± 0.5 V
• Erase and program endurance: 100 times (all areas)
• Program security: ROM code protect and ID code check
• Debug functions: On-chip debug and on-board flash reprogram
Operating Frequency/Supply Voltage 32 MHz: VCC1 = 4.2 to 5.5 V, VCC2 = 3.0 V to VCC1
24 MHz: VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 V to VCC1
Current Consumption
32 mA (32 MHz, VCC1 = VCC2 = 5 V)
23 mA (24 MHz, VCC1 = VCC2 = 3.3 V)
45
μA
(approx. 1 MHz, VCC1 = VCC2 = 3.3 V,
on-chip oscillator low-power consumption mode
→
wait mode)
0.8
μA
(VCC1 = VCC2 = 3.3 V, stop mode)
Operating Ambient Temperature (°C) -20 to 85°C, -40 to 85°C (optional)
(3)
Package
144-pin LQFP (PLQP0144KA-A)
NOTES:
1. IEBus is a registered trademark of NEC Electronics Corporation.
2. Available in UART0.
3. Please contact a Renesas sales office for optional features.
D/A Converter
CRC Calculation Circuit
Specification
Clock synchronous/asynchronous × 5
I
2
C bus, special mode 2, GCI mode, SIM mode,
IrDA mode
(2)
, IEBus (optional)
(1)(3)
Clock synchronous/asynchronous × 2
10-bit resolution × 34 channels (in single-chip mode)
10-bit resolution × 18 channels (in memory expansion mode
and microprocessor mode)
Including sample and hold function
8-bit resolution × 2 channels
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 1.3
Item
CPU
Specifications (100-Pin Package) (1/2)
Function
Central processing
unit
1. Overview
Memory
ROM, RAM, data
flash
Power Supply Voltage Detection
External Bus
Expansion
Bus/memory
expansion function
Specification
M32C/80 core (multiplier: 16 bits × 16 bits
→
32 bits
multiply-addition operation instructions: 16 × 16 + 48
→
48 bits)
• Basic instructions: 108
• Minimum instruction execution time:
31.3 ns (f(CPU) = 32 MHz, VCC1 = 4.2 to 5.5 V)
41.7 ns (f(CPU) = 24 MHz, VCC1 = 3.0 to 5.5 V)
• Operating mode: Single-chip mode, memory expansion mode,
and microprocessor mode
See
Tables 1.5 to 1.7 Product List.
Vdet3 detection function, Vdet4 detection function,
cold start/warm start determination function
• Address space: 16 Mbytes
• External bus interface: 1 to 7 wait states can be inserted,
4 chip select outputs, 3 V and 5 V interfaces
• Bus format: Switchable between separate bus and multiplexed
bus formats, switchable data bus width (8-bit or 16-bit)
• 4 circuits:
Main clock, sub clock, on-chip oscillator,
PLL frequency synthesizer
• Oscillation stop detection:
Main clock oscillation stop detection function
• Frequency divider circuit:
Dividing ratio selectable among 1, 2, 3, 4, 6, 8, 10, 12, 14, 16
• Low power consumption features: Wait mode, stop mode
• Interrupt vectors: 70
• External interrupt inputs: 11 (NMI, INT × 6, key input × 4)
• Interrupt priority levels: 7
15-bit × 1 channel (with prescaler)
• 4 channels, cycle steal method
• Trigger sources: 43
• Transfer modes: 2 (single transfer and repeat transfer)
• Can be activated by all peripheral function interrupt sources
• Transfer modes: 2 (single transfer and burst transfer)
• Immediate transfer, calculation transfer, and chain transfer
functions
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode,
pulse width modulation (PWM) mode,
Event counter 2-phase pulse signal processing (2-phase
encoder input) × 3
16-bit timer × 6
Timer mode, event counter mode, pulse period measurement
mode, pulse width measurement mode
3-phase inverter control × 1 (using timer A1, timer A2, timer A4,
and timer B2)
On-chip dead time timer
Clock
Clock generation
circuits
Interrupts
Watchdog Timer
DMA
DMAC
DMACII
Timer
Timer A
Timer B
Timer function for
3-phase motor
control
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
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M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
Table 1.4
Specifications (100-Pin Package) (2/2)
1. Overview
Item
Function
Serial Interface UART0 to UART4
UART5
A/D Converter
CRC-CCITT (X
16
+ X
12
+ X
5
+ 1) compliant
X/Y Converter
16 bits x 16 bits
Intelligent I/O
16-bit timer × 2
• Time measurement function (input capture): 8 channels
• Waveform generation function (output compare): 10 channels
• Communication function: Clock synchronous mode, clock
asynchronous mode, HDLC data processing mode,
IEBus (optional)
(1)(3)
• 2-phase pulse signal processing (2-phase encoder input) × 1
ROM Correction Function
Address match interrupt × 8
CAN modules
Supporting CAN 2.0B specification
M32C/87: 16 slots × 2 channels, M32C/87A: 16 slots × 1 channel
M32C/87B: none
I/O Ports
Programmable I/O
• Input only: 1
ports
• CMOS I/O: 85, selectable pull-up resistor
• N channel open drain ports: 2
Flash Memory
• Erase and program voltage:
3.3 V ± 0.3 V or 5.0 V ± 0.5 V
• Erase and program endurance: 100 times (all areas)
• Program security: ROM code protect and ID code check
• Debug functions: On-chip debug and on-board flash reprogram
Operating Frequency/Supply Voltage 32 MHz: VCC1 = 4.2 to 5.5 V, VCC2 = 3.0 V to VCC1
24 MHz: VCC1 = 3.0 to 5.5 V, VCC2 = 3.0 V to VCC1
Current Consumption
32 mA (32 MHz, VCC1 = VCC2 = 5 V)
23 mA (24 MHz, VCC1 = VCC2 = 3.3 V)
45
μA
(approx. 1 MHz, VCC1 = VCC2 = 3.3 V,
on-chip oscillator low-power consumption mode
→
wait mode)
0.8
μA
(VCC1 = VCC2 = 3.3 V, stop mode)
Operating Ambient Temperature (°C) -20 to 85°C, -40 to 85°C (optional)
(3)
Package
100-pin LQFP (PLQP0100KB-A)
100-pin QFP (PRQP0100JB-A)
NOTES:
1. IEBus is a registered trademark of NEC Electronics Corporation.
2. Available in UART0.
3. Please contact a Renesas sales office for optional features.
D/A Converter
CRC Calculation Circuit
Specification
Clock synchronous/asynchronous × 5
I
2
C bus, special mode 2, GCI mode, SIM mode,
IrDA mode
(2)
, IEBus (optional)
(1)(3)
Clock synchronous/asynchronous × 1
10-bit resolution × 26 channels (in single-chip mode)
10-bit resolution × 10 channels (in memory expansion mode
and microprocessor mode)
Including sample and hold function
8-bit resolution × 2 channels
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
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