8752CY datasheet, PDF - EEWORLD Datasheet

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8752CY: DescriptionPLL Based Clock Driver, 8752 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.60 MM HEIGHT, MS-026, LQFP-32; Categorylogic logic; File Size136KB，14 Pages; ManufacturerIDT (Integrated Device Technology)

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8752CY Overview

PLL Based Clock Driver, 8752 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.60 MM HEIGHT, MS-026, LQFP-32

8752CY Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	QFP
package instruction	LQFP, QFP32,.35SQ,32
Contacts	32
Reach Compliance Code	not_compliant
ECCN code	EAR99
Other features	ALSO OPERATES AT 3.3V SUPPLY
series	8752
Input adjustment	MUX
JESD-30 code	S-PQFP-G32
JESD-609 code	e0
length	7 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	32
Actual output times	8
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Encapsulate equivalent code	QFP32,.35SQ,32
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	240
power supply	2.5/3.3 V
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.09 ns
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	20
width	7 mm
minfmax	240 MHz
Base Number Matches	1

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ICS8752

KEW

, 1-

-8

LVCMOS C

LOCK

ULTIPLIER

ERO

ELAY

UFFER

ENERAL

ESCRIPTION

The ICS8752 is a low voltage, low skew LVCMOS clock

generator. With output frequencies up to 240MHz, the

ICS8752 is targeted for high performance clock applcations.

Along with a fully integrated PLL, the ICS8752 contains

frequency configurable outputs and an external feedback

input for regenerating clocks with “zero delay”.

Dual clock inputs, CLK0 and CLK1, support redundant clock

applications. The CLK_SEL input determines which refer-

ence clock is used. The output divider values of Bank A and

B are controlled by the DIV_SELA0:1, and DIV_SELB0:1,

respectively.

For test and system debug purposes, the PLL_SEL input

allows the PLL to be bypassed. When HIGH, the MR/nOE

input resets the internal dividers and forces the outputs to

the high impedance state.

The low impedance LVCMOS outputs of the ICS8752 are

designed to drive terminated transmission lines. The

effective fanout of each output can be doubled by

utilizing the ability of each output to drive two series

terminated transmission lines.

EATURES

•

Fully integrated PLL

•

Eight LVCMOS outputs, 7Ω typical output impedance

•

Selectable LVCMOS CLK0 or CLK1 inputs for

redundant clock applications

•

Input/Output frequency range: 18.33MHz to 240MHz

at V

= 3.3V ± 5%

•

VCO range: 220MHz to 480MHz

•

External feedback for “zero delay” clock regeneration

•

Cycle-to-cycle jitter: 75ps (maximum),

(all outputs are the same frequency)

•

Output skew: 100ps (maximum)

•

Bank skew: 55ps (maximum)

•

Full 3.3V or 2.5V supply voltage

•

0°C to 70°C ambient operating temperature

•

Available in both standard and lead-free RoHS-compliant

packages

LOCK

IAGRAM

PLL_SEL

PLL

FB_IN

CLK0

CLK1

CLK_SEL

DIV_SELA1

DIV_SELA0

PHASE

DETECTOR

VCO

÷2

÷4

÷6

÷8

÷12

SSIGNMENT

PLL_SEL

GND

DDO

QB3

QB2

32 31 30 29 28 27 26 25

QA0

QA1

QA2

QA3

DIV_SELB0

DIV_SELB1

DIV_SELA0

DIV_SELA1

MR/nOE

CLK0

QB0

QB1

QB2

QB3

CLK_SEL

DDA

CLK1

GND

QA0

QA1

DDO

9 10 11 12 13 14 15 16

GND

QB1

QB0

DDO

QA3

QA2

GND

ICS8752

GND

FB_IN

DIV_SELB1

DIV_SELB0

MR/nOE

32-Lead LQFP

7mm x 7mm x 1.4mm package body

Y package

Top View

8752CY

www.idt.com

REV. C JULY 2, 2010

8752CY Related Products

	8752CY	8752CYT
Description	PLL Based Clock Driver, 8752 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.60 MM HEIGHT, MS-026, LQFP-32	PLL Based Clock Driver, 8752 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 1.60 MM HEIGHT, MS-026, LQFP-32
Is it lead-free?	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible
Parts packaging code	QFP	QFP
package instruction	LQFP, QFP32,.35SQ,32	LQFP, QFP32,.35SQ,32
Contacts	32	32
Reach Compliance Code	not_compliant	not_compliant
ECCN code	EAR99	EAR99
Other features	ALSO OPERATES AT 3.3V SUPPLY	ALSO OPERATES AT 3.3V SUPPLY
series	8752	8752
Input adjustment	MUX	MUX
JESD-30 code	S-PQFP-G32	S-PQFP-G32
JESD-609 code	e0	e0
length	7 mm	7 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3	3
Number of functions	1	1
Number of terminals	32	32
Actual output times	8	8
Maximum operating temperature	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LQFP	LQFP
Encapsulate equivalent code	QFP32,.35SQ,32	QFP32,.35SQ,32
Package shape	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)	240	240
power supply	2.5/3.3 V	2.5/3.3 V
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.09 ns	0.09 ns
Maximum seat height	1.6 mm	1.6 mm
Maximum supply voltage (Vsup)	2.625 V	2.625 V
Minimum supply voltage (Vsup)	2.375 V	2.375 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	20	20
width	7 mm	7 mm
minfmax	240 MHz	240 MHz

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