7512 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0122-0101
Rev.1.01
Feb 18, 2005
DESCRIPTION
The 7512 Group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 7512 Group is designed for battery-pack and includes serial
interface functions, 8-bit timer, A/D converter, current integrator
and I
2
C-BUS interface.
FEATURES
qBasic
machine-language instructions ...................................... 71
qMinimum
instruction execution time .................................. 1.0
µs
(at 4 MHz oscillation frequency)
qMemory
size
Flash memory .................................................. 36 K to 52 Kbytes
RAM ............................................................... 1.0 K to 1.5 Kbytes
qProgrammable
input/output ports ............................................ 36
qInterrupts
................................................. 19 sources, 16 vectors
qTimers
............................................................................. 8-bit
✕
4
qSerial
interface
Serial I/O1 .......... 8-bit
✕
1 (UART or Clock-synchronized)
Serial I/O2 .......................... 8-bit
✕
1(Clock-synchronized)
qMulti-master
I
2
C-BUS interface (option) ...................... 1 channel
qPWM
............................................................................... 8-bit
✕
1
qA/D
converter ............................................. 10-bit
✕
10 channels
qCurrent
integrator ......................................................... 1 channel
qOver
current detector ................................................... 1 channel
qEasy
thermal sensor .................................................... 1 channel
qWatchdog
timer ............................................................ 16-bit
✕
1
qClock
generating circuit ..................................... Built-in 4 circuits
(high-speed RC oscillator and 32kHz RC oscillator, or connect to
external ceramic resonator or quartz-crystal oscillator)
qPower
source voltage ............................................ 2.45 to 2.55 V
qPower
dissipation
In high-speed mode ...................................................... 3.75 mW
(at 4 MHz oscillation frequency, at 2.5 V power source voltage)
In low-speed mode ........................................................ 1.05 mW
(at 32 kHz oscillation frequency, at 2.5 V power source voltage)
qOperating
temperature range .................................... –20 to 85°C
APPLICATION
Battery-Pack, etc.
P0
7
/PWM
1
/AN
11
PIN CONFIGURATION (TOP VIEW)
P0
1
/S
OUT2
P0
3
/S
RDY2
P0
2
/S
CLK2
P3
4
/AN
4
P3
5
/AN
5
P0
4
/AN
8
P0
0
/S
IN2
P0
5
/AN
9
P0
6
/CFETCNT/AN
10
P1
0
/(LED
0
)
26
36
34
32
31
33
29
35
P3
3
/AN
3
P3
2
/AN
2
P3
1
/AN
1
P3
0
/AN
0
ADV
SS
ADV
RED
V
CC
AV
CC
AV
SS
ISENS
0
ISENS
1
DFETCNT/P4
5
37
38
39
40
41
42
43
44
45
46
47
48
30
28
27
25
P1
1
/(LED
1
)
24
23
22
21
20
P1
2
/(LED
2
)
P1
3
/(LED
3
)
P1
4
/(LED
4
)
P1
5
/(LED
5
)
P1
6
/(LED
6
)
P1
7
/(LED
7
)
V
SS
X
OUT
X
IN
RESET
P2
0
/X
COUT
P2
1
/X
CIN
M37512FCHP
19
18
17
16
15
14
13
10
11
P4
4
/INT
3
/PWM
0
P2
7
/CNTR
0
/S
RDY1
P4
3
/INT
2
/S
CMP2
P2
4
/SDA
2
/R
X
D
P4
0
/CNTR
1
P2
5
/SCL
2
/T
X
D
P2
2
/SDA
1
P2
6
/S
CLK
P2
3
/SCL
1
P4
2
/INT
1
Package type : 48P6Q-A
Fig. 1 M37512FCHP pin configuration
Feb 18, 2005 page 1 of 85
REJ03B0122-0101
P4
1
/INT
0
CNV
SS
12
1
7
3
2
4
5
6
8
9
7512 Group
FUNCTIONAL BLOCK DIAGRAM
Main-clock
input
X
IN
V
SS
V
C
C 43
15
12
18
Main-clock
output
X
OUT
Reset input
RESET
CNV
SS
Feb 18, 2005 page 2 of 85
REJ03B0122-0101
C P U
FUNCTIONAL BLOCK
Fig. 2 Functional block diagram
16
17
Clock generating circuit
X
Prescaler 12 (8)
RAM
ROM
Timer 2 (8)
Timer Y ( 8 )
Timer Y ( 8 )
Y
Prescaler X (8)
A
Timer 2 (8)
X
CIN
sub-clock input
X
COUT
sub-clock output
S
CNTR
0
Prescaler Y (8)
PC
H
PC
L
PS
CNTR
1
Easy thermal
sensor
Watchdog timer
Reset
0
Over current
detector
SI/O1(8)
Current
integrator
I
2
C
(8)
10bit
A/D
converter
PWM (8)
SI/O2(8)
X
CIN
X
COUT
INT
0
- INT
3
P4(6)
P3(6)
P2(8)
P1(8)
P0(8)
ISENS1
35 36 37 38 39 40
AVcc
6 7 8 9 10 11 13 14
19 20 21 22 23 24 25 26
27 28 29 30 31 32 33 34
47 46 45 44
41 42
48 1 2 3 4 5
ISENS0 AVss
ADV
SS
ADV
REF
I/O port P 4
I/O port P 3
I/O port P 2
I/O port P 1
I/O port P 0
7512 Group
PIN DESCRIPTION
Table 1 Pin description
Pin
V
CC
, V
SS
AV
CC
AV
SS
ADV
SS
AD
VREF
CNV
SS
RESET
X
IN
X
OUT
Name
Power source
Analog power
source
Analog reference
voltage
CNV
SS
input
Reset input
Clock input
Clock output
Functions
•Apply voltage of 2.5V to Vcc, and 0 V to Vss.
•Apply voltage of 2.5V to AVcc, and 0 V to AVss, ADVss.
Function except a port function
•Reference voltage input pin for A/D converters.
•This pin controls the operation mode of the chip.
•Normally connected to V
SS
.
•Reset input pin for active “L”.
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the X
IN
and X
OUT
pins to set
the oscillation frequency.
•When a high-speed RC oscillator is used, leave the X
IN
pin and X
OUT
pin open.
•When an external clock is used, connect the clock source to the X
IN
pin and leave the X
OUT
pin open.
• Serial I/O2 function pin
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
•P0
0
to P0
7
are CMOS 3-state output structure,
and P1
0
to P1
7
are N-channel open-drain structure.
•P1
0
to P1
7
(8 bits) are enabled to output large current
for LED drive.
• A/D converter input pin
• A/D converter input pin /
Over current detector function pin
• A/D converter input pin /
PWM output pin
P0
0
/S
IN2
P0
1
/S
OUT2
P0
2
/S
CLK2
P0
3
/S
RDY2
P0
4
/AN
8
P0
5
/AN
9
P0
6
/CFETCNT/
AN
10
P0
7
/AN
11
/
PWM
1
P1
0
–P1
7
P2
0
/X
COUT
P2
1
/X
CIN
P2
2
/SDA
1
P2
3
/SCL
1
P2
4
/SDA
2
/RxD
P2
5
/SCL
2
/TxD
P2
6
/S
CLK
P2
7
/CNTR
0
/
S
RDY1
P3
0
/AN
0
–
P3
5
/AN
5
I/O port P0
I/O port P1
I/O port P2
•8-bit CMOS I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level, but P2
2
to P2
5
can be
switched between CMOS compatible input level or
SMBUS input level in the I
2
C-BUS interface function.
•P2
0
, P2
1
, P2
6
, P2
7
: CMOS3-state output structure.
•P2
2
to P2
5
: N-channel open-drain structure.
• Sub-clock generating circuit I/O
pins (connect a resonat or registor
and capacitor)
• I
2
C-BUS interface function pins
• I
2
C-BUS interface function pins/
Serial I/O1 function pins
• Serial I/O1 function pin
• Serial I/O1 function pin/
Timer X function pin
• A/D converter input pin
I/O port P3
•6-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•CMOS 3-state output structure.
P4
0
/CNTR
1
P4
1
/INT
0
P4
2
/INT
1
P4
3
/INT
2
/S
CMP2
P4
4
/INT
3
/PWM
0
P4
5
/DFETCNT
ISENS0
ISENS1
I/O port P4
•6-bit CMOS I/O port with the same function as port P0.
•CMOS compatible input level.
•P4
0
to P4
2
, P4
5
are CMOS 3-state output structure,
and P4
3
and P4
4
are N-channel open-drain structure.
• Timer Y function pin
• Interrupt input pins
• Interrupt input pin/S
CMP2
output pin
• Interrupt input pin/PWM output pin
• Over current detector function pin
Analog input pin
•Current integrator and over current detector input pins.
•Connect the sense resistor. Normally connect the ISENS0 to GND.
Feb 18, 2005 page 3 of 85
REJ03B0122-0101
7512 Group
GROUP EXPANSION
Renesas plans to expand the 7512 group as follows.
Memory Size
ROM size ........................................................... 36 K to 52 K bytes
RAM size .......................................................... 1024 to 1536 bytes
Memory Type
Support for flash memory version.
Packages
48P6Q-A ............................................... 48-pin plastic molded QFP
Memory Expansion Plan
ROM size (bytes)
60K
Mass production
M37512FC
48K
Under development
M37512FCH
Mass production
M37512F8
32K
Under development
M37512F8H
768
1024
1280
1536
3072
RAM size (bytes)
Fig. 3 Memory expansion plan
Currently planning products are listed below.
Table 2 Support products
Product name
M37512F8HP
M37512F8-XXXHP
M37512F8HHP
M37512F8H-XXXHP
M37512FCHP
(Note 1)
(Note 1)
ROM size (bytes)
RAM size (bytes)
Package
Remarks
32K + 4K
1024
48P6Q-A
M37512FC-XXXHP
48K + 4K
1536
M37512FCHHP
(Note 1)
M37512FCH-XXXHP (Note 1)
Note 1. The products of which erase/write cycles onto the blocks A and B are maximum 10k are under development.
Feb 18, 2005 page 4 of 85
REJ03B0122-0101
7512 Group
FUNCTIONAL DESCRIPTION
CENTRAL PROCESSING UNIT (CPU)
The 7512 Group uses the standard 740 Family instruction set. Re-
fer to the table of 740 Family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “00
16
”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“01
16
”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 5.
Store registers other than those described in Figure 4 with pro-
gram when the user needs them during interrupts or subroutine
calls (see Table 3).
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc. are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PC
H
and PC
L
. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b7
A
b7
X
b7
Y
b7
S
b15
PC
H
b7
b7
PC
L
b0
Accumulator
b0
Index register X
b0
Index register Y
b0
Stack pointer
b0
Program counter
b0
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
N V T B D I Z C
Fig.4 740 Family CPU register structure
Feb 18, 2005 page 5 of 85
REJ03B0122-0101
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