0
R
XC4000XLA/XV Field Programmable
Gate Arrays
0
0*
DS015 (v1.3) October 18, 1999
Product Specification
XC4000XLA/XV Family Features
Note:
XC4000XLA devices are improved versions of
XC4000XL devices. The XC4000XV devices have the
same features as XLA devices, incorporate additional inter-
connect resources and extend gate capacity to 500,000
system gates. The XC4000XV devices require a separate
2.5V power supply for internal logic but maintain 5V I/O
compatibility via a separate 3.3V I/O power supply. For
additional information about the XC4000XLA/XV device
architecture, refer to the XC4000E/X FPGA Series general
and functional descriptions.
• System-featured Field-Programmable Gate Arrays
- Select-RAM
TM
memory: on-chip ultra-fast RAM with
- Synchronous write option
- Dual-port RAM option
- Flexible function generators and abundant flip-flops
- Dedicated high-speed carry logic
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
• Flexible Array Architecture
• Low-power Segmented Routing Architecture
• Systems-oriented Features
- IEEE 1149.1-compatible boundary scan
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- Unlimited reprogrammability
• Read Back Capability
- Program verification and internal node observability
Table 1: XC4000XLA Series Field Programmable Gate Arrays
*
Electrical Features
• XLA Devices Require 3.0 - 3.6 V (VCC)
• XV Devices Require 2.3- 2.7 V (VCCINT)
and 3.0 - 3.6 V (VCCIO)
• 5.0 V TTL compatible I/O
• 3.3 V LVTTL, LVCMOS compliant I/O
• 5.0 V and 3.0 V PCI Compliant I/O
• 12 mA or 24 mA Current Sink Capability
• Safe under All Power-up Sequences
• XLA Consumes 40% Less Power than XL
• XV Consumes 65% Less Power than XL
• Optional Input Clamping to VCC (XLA) or VCCIO (XV)
Additional Features
• Footprint Compatible with XC4000XL FPGAs - Lower
cost with improved performance and lower power
• Advanced Technology — 5 layer metal, 0.25
µm
CMOS
process (XV) or 0.35
µm
CMOS process (XLA)
• Highest Performance — System erformance beyond
100 MHz
• High Capacity — Up to 500,000 system gates and
270,000 synchronous SRAM bits
• Low Power — 3.3 V/2.5 V technology plus segmented
routing architecture
• Safe and Easy to Use — Interfaces to any combination
of 3.3 V and 5.0 V TTL compatible devices
6
Device
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
XC40110XV
XC40150XV
XC40200XV
XC40250XV
Logic
Cells
1,368
1,862
2,432
3,078
3,800
4,598
5,472
7,448
9,728
12,312
16,758
20,102
Max Logic Max. RAM
Typical
Gates
Bits
Gate Range
(No RAM) (No Logic) (Logic and RAM)*
13,000
18,432
10,000 - 30,000
20,000
25,088
13,000 - 40,000
28,000
36,000
44,000
52,000
62,000
85,000
110,000
150,000
200,000
250,000
32,768
41,472
51,200
61,952
73,728
100,352
131,072
165,888
225,792
270,848
18,000 - 50,000
22,000 - 65,000
27,000 - 80,000
33,000 - 100,000
40,000 - 130,000
55,000 - 180,000
75,000 - 235,000
100,000 - 300,000
130,000 - 400,000
180,000 - 500,000
CLB
Matrix
24 x 24
28 x 28
32 x 32
36 x 36
40 x 40
44 x 44
48 x 48
56 x 56
64 x 64
72 x 72
84 x 84
92 x 92
Total
CLBs
576
784
1,024
1,296
1,600
1,936
2,304
3,136
4,096
5,184
7,056
8,464
Number
of
Flip-Flops
1,536
2,016
2,560
3,168
3,840
4,576
5,376
7,168
9,216
11,520
15,456
18,400
Required
Max.
Configur-
User I/O ation Bits
192
393,632
224
521,880
256
288
320
352
384
448
448
448
448
448
668,184
832,528
1,014,928
1,215,368
1,433,864
1,924,992
2,686,136
3,373,448
4,551,056
5,433,888
*
Maximum values of gate range assume 20-30% of CLBs used as RAM
DS015 (v1.3) October 18, 1999 - Product Specification
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XC4000XLA/XV Field Programmable Gate Arrays
The XV devices also incorporate additional routing
resources in the form of 8 octal-length segmented routing
channels vertically and horizontally per row and column.
General Description
XC4000 Series high-performance, high-capacity Field Pro-
grammable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of fifteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, increased speed, abundant
routing resources, and new, sophisticated software to
achieve fully automated implementation of complex,
high-density, high-performance designs.
XLA/XV and XL Family Differences
The XC4000XLA/XV families of FPGAs are logically identi-
cal to XC4000EX and XC4000XL FPGAs, however I/O,
configuration logic, JTAG functionality, and performance
have been enhanced. In addition, they deliver:
•
Improved Performance
XLA/XV devices benefit from advance processing
technology and a reduction in interconnect capacitance
which improves performance over XL devices by more
than 30%.
•
Lower Power
XLA/XV devices have reduced power requirements
compared to equivalent XL devices.
•
Shorter routing delays
The smaller die of XLA/XV devices directly reduces
clock delays and the delay of high-fanout signals. The
reduction in clock delay allows improved pin-to-pin I/O
specifications.
•
Lower Cost
XLA/XV device cost is directly related to the die size
and has been reduced significantly from that of
equivalent XL devices.
•
Express mode configuration
Express mode configuration is available on the XLA and
XV devices.
Figure 1: Cross Section of Xilinx 0.25 micron, 5 layer
metal XC4000XV FPGA.
Visible features are five layers of
metallization, tungsten plug vias and trench isolation. The
small gaps above the lowest layer are 0.25 micron
polysilicon MOSFET gates. The excellent planarity of each
metal layer is due to the use of “chemical-mechanical
polishing” or CMP. In effect, each layer is ground flat before
a new layer is added.
IOB Enhancements
•
12/24 mA Output Drive
The XLA/XV family of FPGAs allow individual IOBs to
be configured as high drive outputs. Each output can be
configured to have 24 mA drive strength as opposed to
the standard default strength of 12 mA.
•
VCC Clamping Diode
XLA and XV FPGAs have an optional clamping diode
connected from each output to VCC (VCCIO for XV).
When enabled they clamp ringing transients back to the
3.3V supply rail. This clamping action is required in
3.3V PCI applications. VCC clamping is a global option
affecting all I/O pins. If enabled, TTL I/O compatibility is
maintained, but full 5.0 Volt I/O tolerance is sacrificed.
•
Enhanced ESD protection
An improved ESD structure allows XV devices to safely
pass the stringent 5V PCI (4.2.1.3) ringing test. This
test applies an 11V pulse to each IOB for 11 ns via a 55
ohm resistor.
•
Full 3.3V and 5.0V PCI compliance
The addition of 12/24 mA drive, optional 3.3V clamping
and improved ESD provides full compliance with either
3.3V or 5.0V PCI specifications.
Technology Advantage
XC4000XLA/XV FPGAs use 5 layer metal silicon technol-
ogy to improve performance while reducing device cost and
power. In addition, IOB enhancements provide full PCI
compliance and the JTAG functionality is expanded.
Low Power Internal Logic
XC4000XV FPGAs incorporate all the features of the XLA
devices but require a separate 2.5V power supply for inter-
nal logic. I/O pads are still driven from a 3.3V power supply.
The 2.5V logic supply is named VCCINT and the 3.3 V IO
supply is named VCCIO.
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XC4000XLA/XV Field Programmable Gate Arrays
Three-State Register
XC4000XLA/XV devices incorporate an optional register
controlling the three-state enable in the IOBs.The use of
the three-state control register can significantly improve
output enable and disable time.
Table 2: K-Factor and Relative Power.
Power
Power
Relative To Relative To
XL
XLA
1.00
1.65
0.60
1.00
0.35
0.58
FastCLK Clock Buffers
The XLA/XV devices incorporate FastCLK clock buffers.
Two FastCLK buffers are available on each of the right and
left edges of the die. Each FastCLK buffer can provide a
fast clock signal (typically < 1.5 ns clock delay) to all the
IOBs within the IOB octant containing the buffer. The Fast-
CLK buffers can be instantiated by use of the BUFFCLK
symbols. (In addition to FastCLK buffers, the Global Early
BUFGE clock buffers #1, #2, #5, and #6 can also provide
fast clock signals (typically < 1.5 ns clock delay) to IOBs on
the top and bottom of the die.
FPGA Family
XC4000XL
XC4000XLA
XC4000XV
K-Factor
28
17
13
XLA/XV Logic Performance
XC4000XLA/XV devices feature 30% faster device speed
than XL devices, and consistent performance is achieved
across all family members.
Table 3
illustrates the perfor-
mance of the XLA devices. For details regarding the imple-
mentation of these benchmarks refer to XBRF15 “Speed
Metrics for High Performance FPGAs”.
Table 3: XLA/XV Estimated Benchmark Performance
Register - Register
Benchmarks
Adder
2 Cascaded Adders
4 Cascaded Adders
Size
8-Bit
16-Bit
32-Bit
16-Bit
16-Bit
1 Level
2 Level
4 Level
6 Level
1 CLBs
4 CLBs
16 CLBs
64 CLBs
128 CLBs
8-Bits by 16
8-Bits by 256
Maximum
Frequency
172 MHz
144 MHz
108 MHz
94 MHz
57 MHz
314 MHz
193 MHz
108 MHz
75 MHz
325 MHz
260 MHz
185 MHz
108 MHz
81 MHz
172 MHz
172 MHz
XLA/XV Power Requirements
XC4000XLA devices require 40% less power per CLB than
equivalent XL devices. XC4000XV devices require 42%
less power per CLB than equivalent XLA devices and 65%
less power than XL devices The representative K-Factor for
the following families can be found in
Table 2.
The K-Factor
predicts device current for typical user designs and is
based on filling the FPGA with active 16-Bit counters and
measuring the device current at 1 MHz. This technique is
described in XBRF14 “A Simple Method of Estimating
Power in XC4000XL/EX/E FPGAs”. To predict device
power (P) using the K-Factor use the following formula:
P=V*K*N*F; where:
P= Device Power
V= Power supply voltage
K= the Device K-Factor
N = number of active registers
F = Frequency in MHz
6
Cascaded 4LUTs
Interconnect
(Manhattan Distance)
Dual Port RAM
(Pipelined)
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XC4000XLA/XV Field Programmable Gate Arrays
•
BUFGE (I,O)
- The Global Early Buffer
•
BUFGLS (I,O)-
The Global Low Skew Buffer
•
BUFFCLK (I,O)
- The FastCLK Buffer
•
ILFFX (D, GF, CE, C, Q)
- The Fast Capture Latch
Macro
Locating I/O elements
- It is necessary to connect these
elements to a particular I/O pad in order to select which
buffer or fast capture latch will be used.
Restricted Clock Loading
- Because the input hold
requirement is a function of internal clock delay, it may be
necessary to restrict the routing of BUFGE to IOBs along
the top and bottom of the die to obtain sub-ns clock delays.
BUFGE 1
BUFGE 6
Using Fast I/O CLKS
There are several issues associated with implementing fast
I/O clocks by using multiple FastCLK and BUFGE clock
buffers for I/O transfers and a BUFGLS clock buffer for
internal logic.
Reduced Clock to Out Period
- When transferring data
from a BUFGLS clocked register to an IOB output register
which is clocked with a fast I/O clock, the total amount of
time available for the transfer is reduced.
Using Fast Capture Latch in IOB input -
It is necessary to
transfer data captured with the fast I/O clock edge to a
delayed BUFGLS clock without error. The use of the Fast
Capture Latch in the IOBs provides this functionality.
Driving multiple clock inputs
- Since each FastCLK input
can only reach one octant of IOBs it will usually be neces-
sary to drive multiple FastCLK and BUFGE input pads with
a copy of the system clock. Xilinx recommends that sys-
tems which use multiple FastCLK and BUFGE input buffers
use a “Zero Delay” clock buffer such as the Cypress
CY2308 to drive up to 8 input pins. These devices contain a
Phase locked loop to eliminate clock delay, and specify less
than 250ps output jitter.
PCB layout
- The recommended layout is to place the PLL
underneath the FPGA on the reverse side of the PCB. All 8
clock lines should be of equal length. This arrangement will
allow all the clock line to be less than 2 cm in length which
will generally eliminate the need for clock termination.
Advancing the FPGAs clock -
An additional advantage to
using a PLL-equipped clock buffer is that it can advance the
FPGA clocks relative to the system clock by incorporating
additional board delay in the feedback path. Approximately
6 inches of trace length are necessary to delay the signal
by 1 ns.
Advancing the FPGA’s clock directly reduces input hold
requirements and improves clock to out delay. FPGA clocks
should not be advanced more than the guaranteed mini-
mum Output Hold Time (minus any associated clock jitter)
or the outputs may change state before the system clock
edge. For XLA and XV FPGAs the Output Hold Time is
specified as a minimum Clock to Output Delay in the tables
in the respective family Electrical Specification sections.
The maximum recommended clock advance equals this
value minus any clock jitter.
Instantiating I/O elements-
Depending on the design
environment, it may be necessary to instantiate the fast I/O
elements. They are found in the libraries as:
FCLK 1
FCLK 4
FCLK 2
BUFGLS 2
BUFGE 2
FCLK 3
BUFGE 5
Figure 2: Location of FastCLK, BUFGE and BUFGLS
Clock Buffers in XC4000XLA/XV FPGAs
SysClk
PLL
Clock
O0
Buffer
O1
O2
O3
O4
O5
FB
O6
Ref
O7
BUFGE
1
BUFGE
2
BUFGE
5
BUFGE
6
FCLK1
FCLK2
FCLK3
FCLK4
XC4000XLA
XC4000XV
Figure 3: Diagram of XC4000XLA/XV FPGA
Connected to PLL Clock Buffer Driving 4 BUFGE and
4 FastCLK Clock Buffers.
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XC4000XLA/XV Field Programmable Gate Arrays
JTAG Enhancements
XC4000XLA/XV devices have improved JTAG functionality
and performance in the following areas:
•
IDCODE
- The IDCODE register in JTAG is now
supported. All future Xilinx FPGAs will support the
IDCODE register. By using the IDCODE, the device
connected to the JTAG port can be determined. The
use of the IDCODE enables selective configuration
dependent upon the FPGA found. The IDCODE register
has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
Where:
c = the company code;
a = the array dimension in CLBs;
f = the Family code;
v = the die version number
Family Codes = 01 for XLA;
= 02 for SpartanXL;
= 03 for Virtex;
= 07 for XV.
Xilinx company code = 49 (hex)
Table 4: IDCODEs assigned to XC4000XLA/XV FPGAs
FPGA
XC4013XLA
XC4020XLA
XC4028XLA
XC4036XLA
XC4044XLA
XC4052XLA
XC4062XLA
XC4085XLA
XC40110XV
XC40150XV
XC40200XV
XC40250XV
IDCODE
0x00218093
0x0021c093
0x00220093
0x00224093
0x00228093
0x0022c093
0x00230093
0x00238093
0x00e40093
0x00e48093
0x00e54093
0x00e5c093
•
Bypass FF -
Bypass FF and IOB is modified to provide
DRCLOCK only during BYPASS for the bypass flip-flop
and during EXTEST or SAMPLE/PRELOAD for the IOB
register.
XV and XLA Family Differences
The high density of the XC4000XV family FPGAs is
achieved by using advanced 0.25 micron silicon technol-
ogy. A 2.5 Volt power supply (VCCINT) is necessary to pro-
vide the reduced supply voltage required by 0.25 micron
internal logic, however to maintain TTL compatibility a 3.3V
power supply (VCCIO) is required by the I/O.
To accommodate the higher gate capacity of XV devices,
additional interconnect has been added. These differences
are detailed below.
•
VCCINT (2.5 Volt) Power Supply Pins
The XV family of FPGAs requires a 2.5V power supply
for internal logic, which is named VCCINT. The pins
assigned to the VCCINT supply are named in the pinout
guide for the XC4000XV FPGAs and in
Table 5 on page
162.
•
VCCIO (3.3 Volt) Power Supply Pins
Both the XV and XLA FPGAs use a 3.3V power supply
to power the I/O pins. The I/O supply is named VCCIO
in the XV family.
•
Octal-Length Interconnect Channels
The XC40110XV, XC40150XV, XC40200XV, and
XC40250XV have enhanced routing. Eight routing
channels of octal length have been added to each CLB
in both vertical and horizontal dimensions.
6
XLA-to-XL Socket Compatibility
The XC4000XLA devices are generally available in the
same packages as equivalent XL devices, however the
range of packages available for the XC4085XLA has been
extended to include smaller packages such as the HQ240.
XV-to-XL/XLA Socket Compatibility
XC4000XV devices are available in five package options,
pin-grid PG599 and ball-grid BG560, BG432, and BG352
and quad-flatpack HQ240. With the exception of the
VCCINT power pins, XC4000XV FPGAs are compatible
with XL and XLA devices in these packages if the following
guidelines are followed:
• Lay out the PCB for the XV pinout.
• When an XL or XLA device is installed disconnect the
VCCINT (2.5 V) supply. For the PG599, VCCINT should
be connected to 3.3V. For BG560, BG432 and BG352
and HQ240 packages, the VCCINT voltage source
should be left unconnected. The unused I/O pins in the
XL/XLA devices connected to VCCINT will be pulled up
to 3.3V. Care must be taken to insure that these pins
are not driven when the XL/XLA device is operative.
• When an XC4000XV is installed, the VCCINT pins must
•
Configuration State
- The configuration state is
available to JTAG controllers.
•
Configure Disable
- The JTAG port can be prevented
from reconfiguring the FPGA
•
TCK Startup
- TCK can now be used to clock the
start-up block in addition to other user clocks.
•
CCLK holdoff
- Changed the requirement for Boundary
Scan Configure or EXTEST to be issued prior to the
release of INIT pin and CCLK cycling.
•
Reissue configure
- The Boundary Scan Configure
can be reissued to recover from an unfinished attempt
to configure the device.
DS015 (v1.3) October 18, 1999 - Product Specification
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