IDT71V2576S166BG8 datasheet, PDF

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IDT71V2576S166BG8: DescriptionCache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, BGA-119; Categorystorage storage; File Size359KB，20 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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IDT71V2576S166BG8 Overview

Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, BGA-119

IDT71V2576S166BG8 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.5 ns
JESD-30 code	R-PBGA-B119
JESD-609 code	e3
length	22 mm
memory density	4718592 bit
Memory IC Type	CACHE SRAM
memory width	36
Humidity sensitivity level	1
Number of functions	1
Number of terminals	119
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX36
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	MATTE TIN
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	14 mm
Base Number Matches	1

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128K X 36, 256K X 18

3.3V Sychronous SRAMs

2.5V I/O, Pipelined Outputs,

Burst Counter, Single Cycle Deselect

Preliminary

IDT71V2576

IDT71V2578

Features

128K x 36, 256K x 18 memory configurations

Supports high system speed:

200MHz 3.1ns clock access time

183MHz 3.3ns clock access time

166MHz 3.5ns clock access time

150MHz 3.8ns clock access time

133MHz 4.2ns clock access time

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte write

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O

Packaged in a JEDEC Standard 100-lead plastic thin quad

flatpack (TQFP) and 119-lead ball grid array (BGA)

Description

The IDT71V2576/78 are high-speed SRAMs organized as 128K x

36/256K x 18. The IDT71V2576/78 SRAMs contain write, data, address

and control registers. Internal logic allows the SRAM to generate a self-

timed write based upon a decision which can be left until the end of the write

cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V2576/78 can provide four cycles of data

for a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will be pipelined for one

cycle before it is available on the next rising clock edge. If burst mode

operation is selected (ADV=LOW), the subsequent three cycles of output

data will be available to the user on the next three rising clock edges. The

order of these three addresses are defined by the internal burst counter

and the

LBO

input pin.

The IDT71V2576/78 SRAMs utilize IDTs latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-lead thin plastic quad flatpack (TQFP) as well as a 119-lead ball grid

array (BGA).

Pin Description Summary

-A

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

4876 tbl 01

NOTE:

and

are not applicable for the IDT71V2578.

SEPTEMBER 1999

DSC-4876/5

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