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APVV-FREQ-S-P1-T

Description
PECL Output Clock Oscillator, 38MHz Min, 640MHz Max, CERAMIC, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size1MB,2 Pages
ManufacturerAbracon
Websitehttp://www.abracon.com/index.htm
Environmental Compliance  
Download Datasheet Parametric View All

APVV-FREQ-S-P1-T Overview

PECL Output Clock Oscillator, 38MHz Min, 640MHz Max, CERAMIC, SMD, 6 PIN

APVV-FREQ-S-P1-T Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Reach Compliance Codecompliant
Other featuresTRI-STATE; ENABLE/DISABLE FUNCTION; COMPLEMENTARY O/P; TAPE AND REEL
maximum descent time1.5 ns
Frequency Adjustment - MechanicalNO
Frequency offset/pull rate50 ppm
frequency stability20%
linearity10%
Manufacturer's serial numberAPVV
Installation featuresSURFACE MOUNT
Maximum operating frequency640 MHz
Minimum operating frequency38 MHz
Maximum operating temperature70 °C
Minimum operating temperature
Oscillator typePECL
physical size7.0mm x 5.0mm x 1.8mm
longest rise time1.5 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.25 V
surface mountYES
maximum symmetry55/45 %
Base Number Matches1
CERAMIC SMD VOLTAGE CONTROL CRYSTAL OSCILLATOR
APVV SERIES
: PRELIMINARY
FEATURES:
• Sub 1pS ( 12kHz - 20MHz )
• CMOS, PECL or LVDS Output
• Low Jitter
• Low Power
( 2.5, 3.3V )
• Wide Pull Range
APPLICATIONS:
• SONET, Fiber Channel, SERDES
HDTV, OBSAI, CPRI, PCI Express,
1394
5.0 x 7.0 x 1.8mm
| | | | | | | | | | | | | | |
STANDARD SPECIFICATIONS:
PARAMETERS
Frequency Range
Operating Temperature
Storage Temperature
Frequency Pull Range
Pull Range Linearity
Overall Frequency Stability
Supply Voltage (Vdd)
Phase Jitter RMS
(12KHz-20MHz)
Period Jitter (peak to peak)
Tri-State Function
PECL
65mA max (for 38MHz<Fo<320MHz), 90mA max (320MHz<Fo<640MHz)
Supply Current (I
DD
)
Symmetry (Duty Cycle)
45% min, 50% typical, 55% max.
Output Logic High
V
DD
-1.025V min, V
DD
-0.880V max.
Output Logic Low
V
DD
-1.810V min, V
DD
-1.620V max.
Rise time
1.5ns max, 0.6nSec typical
Fall time
1.5ns max, 0.6nSec typical
CMOS
30mA max (38MHz<Fo<320MHz)
Supply Current
45% min, 50% typ, 55% max,
Symmetry (Duty Cycle)
Rise/ Fall Time
(0.3V ~ 3.0V w/15 pF load) 0.7nS Typ.; (20%-80% w/50Ω Load) 0.3nS Typ.
LVDS
45mA max(for 38MHz<Fo<320MHz), 70mA max (320MHz<Fo<640MHz)
Supply Current (I
DD
)
Output Clock Duty Cycle @ 1.25V
45% min, 50% typical, 55% max
Output Differential Voltage (V
OD
)
247mV min, 355mV typical, 454mV max
VDD Magnitude Change (∆V
OD
)
-50mV min, 50mV max
Output High Voltage
V
OH
= 1.6V max, 1.4V typical
Output Low Voltage
V
OL
= 0.9V min, 1.1V typical
Offset Voltage [R
L
= 100Ω]
V
OS
= 1.125V min, 1.2V typical, 1.375V max
Offset Magnitude Voltage[RL = 100Ω]
∆V
OS
= 0mV min, 3mV typical, 25mV max
Power-off Leakage (I
OXD
) [Vout=VDD or GND, VDD=0V]
±10µA max, ±1µA typical
Differential Clock Rise Time (t
r
) [R
L
=100Ω, CL=10pF]
0.7ns typical, 1.0ns max
Differential Clock Fall Time (t
f
) [R
L
=100Ω, CL=10pF]
0.7ns typical, 1.0ns max
ABRACON IS
ISO 9001 / QS 9000
ISO 9001:2008
CERTIFIED
38 MHz to 640 MHz
0°C to + 70°C (see options)
-55°C to +125°C
± 50 ppm (see options)
10% Max
± 50 ppm max. (see options)
2.25V to 3.63 (2.5V to 3.3V ± 10%)
0.5pS Typ, 1pS Max
20pS typ., 30pS max up to 320 MHz; 50pS typ., 70pS max 321MHz to 640MHz
For CMOS and LVDS
= "1" (VIH ³ 0.7* Vdd) or open: Oscillation;
"0" (VIL < 0.3* Vdd): No oscillation/Hi Z
For PECL (See TriState Pin Operation table) = P Option (Standard PECL OE)
"0" (VIL < 0.3* Vdd): or Open: Oscillation; "1" (VIH ³ 0.7* Vdd): No oscillation/Hi Z
P1 Option
= "1" (VIH ³ 0.7* Vdd) or open: Oscillation;
"0" (VIL < 0.3* Vdd): No oscillation/Hi Z
30332 Esperanza, Rancho Santa Margarita, California 92688
tel 949-546-8000
|
fax 949-546-8001
| www.abracon.com
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