Integrated
Circuit
Systems, Inc.
ICS9148-111
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
Recommended Application:
ALI (Aladdin V
) mobile.
Output Features:
•
3 - CPUs @ 2.5V/3.3V, up to 100MHz.
•
3 - AGPCLK @ 3.3V
•
13 - SDRAM @ 3.3V, up to 100MHz.
•
6 - PCI @ 3.3V, including one free running.
•
1 - 48MHz, @ 3.3V fixed.
•
1 - REF @ 3.3V, 14.318MHz.
Features:
•
Up to 100MHz frequency support
•
Support power management: CPU, PCI, AGP stop and,
Power down Mode from I
2
C programming.
•
Spread spectrum for EMI control (0 to -0.6%, ± 0.25%).
•
Uses external 14.318MHz crystal
•
FS pins for frequency select
Key Specifications:
•
CPU – CPU:
<250ps
•
SDRAM - SDRAM:
<250ps
•
AGP-AGP:
<250ps
•
PCI – PCI:
<500ps
•
CPU-SDRAM <500ps
•
CPU(early)-PCI: 1-4ns, Center 2-6ns
•
CPU-AGP
<500ps
Pin Configuration
48-Pin 300mil SSOP
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
Block Diagram
Functionality
CPU,
PCI
AGP
FS2 FS1 FS0 SDRAM (MHz) (MHz)
(MHz)
1
1
1
100
33.33 66.67
1
1
0
95.25
31.75 63.50
1
0
1
83.3
33.30 66.60
1
0
0
75
30.00 60.00
0
1
1
91.5
30.50 61.00
0
1
0
96.22
32.07 64.15
0
0
1
66.8
33.40 66.80
0
0
0
60
30.00 60.00
REF,
IOAPIC
(MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
9148-111 Rev A 10/19/99
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9148-111
Pin Configuration
PIN NUMBER
1
2
3,9,16,22,27,
33,39,45
4
5
6
7
FS1
1, 2
8
10, 11, 12, 13
14
15
17
PCICLK0
FS2
1, 2
PCICLK(1:4)
VDD5
BUFFERIN
CPU_STOP#
1
SDRAM 11
18
28, 29, 31, 32, 34,
35,37,38
20
PCI_STOP#
1
SDRAM 10
SDRAM (0:9)
AGP_STOP#
SDRAM9
21
19,30,36
23
24
25
MODE
1, 2
48MHz
26
41, 43, 44
40
42
46, 47
48
FS0
1, 2
CPUCLK(0:3)
SDRAM12
VDDL
AGP (1:2)
VDD4
IN
OUT
IN
OUT
OUT
PWR
OUT
PWR
PD#
SDRAM8
VDD3
SDATA
SCLK
AGP0
IN
OUT
IN
OUT
PWR
IN
IN
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
PWR
IN
IN
OUT
P I N NA M E
VDD1
REF0
C P U 3 . 3 # _ 2 . 5
1,2
GND
X1
X2
VDD2
PCICLK_F
TYPE
PWR
OUT
IN
PWR
IN
OUT
PWR
OUT
DESCRIPTION
Ref (0:2), XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.
Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V
C P U
1
. L a t c h e d i n p u t
2
Ground
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew
(CPU early) This is not affected by PCI_STOP#
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Frequency select pin. Latched Input
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Supply for fixed PLL, 48MHz, AGP0
Input pin for SDRAM buffers.
Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile
Mode, MODE=0)
SDRAM clock output
Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode,
MODE=0)
SDRAM clock output
SDRAM clock outputs.
This asynchronous input halts AGP(1:2) clocks at logic "0" level when input
low (in Mobile Mode, MODE=0) Does not affect AGP0
SDRAM clock output
This asyncheronous Power Down input Stops the VCO, crystal & internal
clocks when active, Low. (In Mobile Mode, MODE=0)
SDRAM clock output
Supply for SDRAM (0:11), CPU Core, 48MHz clocks,
nominal 3.3V.
Data input for I
2
C serial input.
Clock input of I
2
C input
Advanced Graphic Port output, powered by VDD4. Not affected by
AGP_STOP#
Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
48MHz output clock for USB timing.
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Feedback SDRAM clock output.
Supply for CPU (0:3), either 2.5V or 3.3V nominal
Advanced Graphic Port outputs, powered by VDD4.
Supply for AGP (0:2)
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS9148-111
General Description
The
ICS9148-111
is a single chip clock solution for Desktop/
Notebook designs using the ALI (Aladdin V ) mobile style
chipset. It provides all necessary clock signals for such a
system.
Spread spectrum may be enabled through I
2
C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The
ICS9148-111
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions,
stop clock programming and frequency selection.
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:12), supply for PLL core
VDD4 = AGP (1:2)
VDD5 = Fixed PLL, 48MHz , AGP0
VDDL = CPUCLK (0:2)
Mode Pin - Power Management Input Control
MODE, Pin 25
(Latched Input)
0
1
Pin 17
CPU_STOP#
(INPUT)
SDRAM 11
(OUTPUT)
Pin 18
PCI_STOP#
(INPUT)
SDRAM 10
(OUTPUT)
Pin 20
AGP_STOP#
(INPUT)
SDRAM 9
(OUTPUT)
Pin 21
PD#
(INPUT)
SDRAM 8
(OUTPUT)
Power Management Functionality
AGP_STOP# CPU_STOP# PCI_STOP#
1
1
1
0
0
1
1
1
1
1
0
1
AGP,
CPUCLK
Outputs
Stopped Low
Running
Running
Running
PCICLK
(0:5)
Running
Running
Stopped Low
Running
PCICLK_F,
REF, 48MHz
and SDRAM
Running
Running
Running
Running
Crystal
OSC
Running
Running
Running
Running
VCO
Running
Running
Running
Running
AGP(1:2)
Running
Running
Running
Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5
Input level
(Latched Data)
1
0
Buffer Selected for
operation at:
2.5V VDD
3.3V VDD
Third party brands and names are the property of their respective owners.
3
ICS9148-111
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will
acknowledge
each byte
one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends first byte
(Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2
(H)
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
ACK
Stop Bit
ACK
Byte 5
ACK
Byte 4
ACK
Byte 3
ACK
Byte 2
ACK
Byte 1
ACK
Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3
(H)
ICS (Slave/Receiver)
ACK
ACK
Byte Count
Notes:
1.
2.
3.
4.
5.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
6.
Third party brands and names are the property of their respective owners.
4
ICS9148-111
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 7
Description
Must be 0 for normal operation
0 -- +/- 0.25% Spread Spectrum Modulation
1 -- +/- 0.6% Spread Spectrum Modulation
Bit6 Bit5 Bit4
CPU Clock
PCI
100
33.33
111
95.25
31.75
110
83.3
33.30
101
75
30.00
100
91.5
30.50
011
96.22
32.07
010
66.8
33.40
001
60
30.00
000
0 - Frequency is selected by hardware select, Latched inputs
1 - Frequency is selected by Bit 6:4 (above)
Must be 0 for normal operation
0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1 - Tristate all outputs
PWD
0
AGP
66.67
63.50
66.60
60.00
61.00
64.15
66.80
60.00
Bit 6:4
Note 1
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
Note 1.
Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 000, and if
bit 3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycle.
Note:
PWD = Power-Up Default
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
40
-
41
43
44
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
SDRAM12 (Act/Inact)
(Reserved)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
7
-
13
12
11
10
8
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
PCICLK_F (Act/Inact)
(Reserved)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Third party brands and names are the property of their respective owners.
5
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