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74AUP1G373GN,132

Description
74AUP1G373 - Low-power D-type transparent latch; 3-state SON 6-Pin
Categorylogic    logic   
File Size297KB,22 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Download Datasheet Parametric Compare View All

74AUP1G373GN,132 Overview

74AUP1G373 - Low-power D-type transparent latch; 3-state SON 6-Pin

74AUP1G373GN,132 Parametric

Parameter NameAttribute value
Brand NameNexperia
Parts packaging codeSON
package instructionSON,
Contacts6
Manufacturer packaging codeSOT1115
Reach Compliance Codecompliant
seriesAUP/ULP/V
JESD-30 codeR-PDSO-N6
JESD-609 codee3
length1 mm
Logic integrated circuit typeD LATCH
Humidity sensitivity level1
Number of digits1
Number of functions1
Number of terminals6
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSON
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
propagation delay (tpd)25.9 ns
Maximum seat height0.35 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)0.8 V
Nominal supply voltage (Vsup)1.1 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceTin (Sn)
Terminal formNO LEAD
Terminal pitch0.3 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typeHIGH LEVEL
width0.9 mm
Base Number Matches1
74AUP1G373
Rev. 7 — 27 March 2020
Low-power D-type transparent latch; 3-state
Product data sheet
1. General description
The 74AUP1G373 provides the single D-type transparent latch with 3-state output. While the
latch-enable (LE) input is high, the Q output follows the data (D) input. When pin LE is LOW,
the latch stores the information that was present at the D-input one set-up time preceding the
HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the latch is available at
the (Q) output. When pin OE is HIGH, the output goes to the high-impedance OFF-state. Operation
of input pin OE does not affect the state of the latch.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times
across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire V
CC
range
from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry
disables the output, preventing the damaging backflow current through the device when it is
powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP1G373GN,132 Related Products

74AUP1G373GN,132 74AUP1G373GM,132 74AUP1G373GS,132
Description 74AUP1G373 - Low-power D-type transparent latch; 3-state SON 6-Pin 74AUP1G373 - Low-power D-type transparent latch; 3-state SON 6-Pin 74AUP1G373 - Low-power D-type transparent latch; 3-state
Brand Name Nexperia Nexperia Nexperia
package instruction SON, VSON, VSON,
Manufacturer packaging code SOT1115 SOT886 SOT1202
Reach Compliance Code compliant compliant compliant
series AUP/ULP/V AUP/ULP/V AUP/ULP/V
JESD-30 code R-PDSO-N6 R-PDSO-N6 S-PDSO-N6
JESD-609 code e3 e3 e3
length 1 mm 1.45 mm 1 mm
Logic integrated circuit type D LATCH D LATCH D LATCH
Humidity sensitivity level 1 1 1
Number of digits 1 1 1
Number of functions 1 1 1
Number of terminals 6 6 6
Maximum operating temperature 125 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Output characteristics 3-STATE 3-STATE 3-STATE
Output polarity TRUE TRUE TRUE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SON VSON VSON
Package shape RECTANGULAR RECTANGULAR SQUARE
Package form SMALL OUTLINE SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 260 260 NOT SPECIFIED
propagation delay (tpd) 25.9 ns 25.9 ns 25.9 ns
Maximum seat height 0.35 mm 0.5 mm 0.35 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 0.8 V 0.8 V 0.8 V
Nominal supply voltage (Vsup) 1.1 V 1.2 V 1.1 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal surface Tin (Sn) Tin (Sn) Tin (Sn)
Terminal form NO LEAD NO LEAD NO LEAD
Terminal pitch 0.3 mm 0.5 mm 0.35 mm
Terminal location DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED 30 NOT SPECIFIED
Trigger type HIGH LEVEL POSITIVE EDGE HIGH LEVEL
width 0.9 mm 1 mm 1 mm
Base Number Matches 1 1 1
Parts packaging code SON SON -
Contacts 6 6 -
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