MULTI-ISSUE
64-BIT MICROPROCESSOR
79RC5000
Features
Dual issue super-scalar execution core
– 250 MHz frequency
– Dual issue floating-point ALU operations with other instruction
classes
– Traditional 5-stage pipeline, minimizes load and branch laten-
cies
◆
Single-cycle repeat rate for most floating point ALU
operations
◆
High level of performance for a variety of applications
– High-performance 64-bit integer unit achieves 330 dhrystone
MIPS (dhrystone 2.1)
– Ultra high-performance floating-point accelerator, directly
implementing single- and double-precision operations
achieves 500mflops
– Extremely large on-chip primary cache
– On-chip secondary cache controller
◆
MIPS-IV 64-bit ISA for improved computation
– Compound floating-point operations for 3D graphics and
floating-point DSP
– Conditional move operations
◆
Large on-chip TLB
◆
Active power management, including use of WAIT operation
◆
Large, efficient on-chip caches
– 32KB Instruction Cache, 32KB Data Cache
– 2-set associative in each cach
– Virtually indexed and physically tagged to minimize cache
flushes
– Write-back and write-through selectable on a per page basis
– Critical word first cache miss processing
– Supports back-to-back loads and stores in any combination at
full pipeline rate
◆
High-performance memory system
– Large primary caches integrated on-chip
– Secondary cache control interface on-chip
– High-frequency 64-bit bus interface runs up to 125MHz
– Aggregate bandwidth of on-chip caches, system interface of
5.6GB/s
– High-performance write protocols for graphics and data
communications
◆
Compatible with a variety of operating systems
– Windows™ CE
– Numerous MIPS-compatible real-time operating systems
◆
Uses input system clock, with processor pipeline clock
multiplied by a factor of 2-8
◆
Industrial and commercial temperature range
◆
Block Diagram
Phase Lock Loop
Data Set A
Store Buffer
SysAD
Write Buffer
Read Buffer
Data Set B
DBus
Control
Floating Point Register File
Unpacker/Packer
Floating-point Control
FPIBus
Tag
AuxTag
Load Aligner
Joint TLB
Coprocessor 0
System/Memory
Control
DVA
Integer Control
Integer Register File
Integer/Address Adder
Data TLB Virtual
Shifter/Store Aligner
Logic Unit
ABus
Integer Multiply, Divide
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Tag B
Instruction Set B
IntIBus
Data Tag A
DTLB Physical
Instruction Select
Integer Instruction Register
FP Instruction Register
Instruction Set A
Floating Point
MAdd,Add,Sub, Cvt
Div, SqRt
IVA
PC Incrementer
Branch Adder
Instruction TLB Virtual
Program Counter
The IDT logo is a trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Inte-
grated Device Technology, Inc.
1 of 15
©
2001 Integrated Device Technology, Inc.
April 10, 2001
DSC 5719
79RC5000
DESCRIPTION
The RC5000 serves many performance critical embedded applica-
tions, such as high-end internetworking systems, color printers, and
graphics terminals.
The RC5000 is optimized for high-performance applications, with
special emphasis on system bandwidth and floating point operations,
through integration of high-performance computational units and a high-
performance memory hierarchy. For this class of application, the result
is a relatively low-cost CPU capable of approximately 330 Dhrystone
MIPS.
IDT’s objectives in offering the RC5000 include:
◆
Offering a high performance upgrade path to existing embedded
customers in the internetworking, office automation and
visualization markets.
◆
Providing a significant improvement in the floating- point
performance currently available in a moderately priced MIPS
CPU.
◆
Providing improvements in the memory hierarchy of desktop
systems by using large primary caches and integrating a
secondary cache controller.
◆
Enabling improvements in performance through the use of the
MIPS-IV ISA.
Instruction Set Architecture
The RC5000 implements the MIPS-IV 64-bit ISA, including CP1 and
CP1X functional units (and their instruction set).
Integer Pipeline
The RC5000 is a limited dual-issue machine that utilizes a traditional
5-stage integer pipeline. This basic integer pipeline of the RC5000 is
illustrated in Figure 1. The integer instruction execution speed is tabu-
lated (in number of pipeline clocks) as follows:
Operation
Load
Store
MULT/MULTU
DMULT/DMULTU
DIV/DIVU
DDIV/DDIVU
Other Integer ALU
Branch
Jump
2
2
8
12
36
68
1
2
2
Latency
1
1
8
12
36
68
1
2
2
Repeat
Instruction Issue Mechanism
The RC5000 recognizes two general classes of instructions for multi-
issue:
◆
Floating-point ALU
◆
All others
These instruction classes are pre-decoded by the RC5000, as they
are brought on-chip. The pre-decoded information is stored in the
instruction cache.
Assuming that there are no pending resource conflicts, the RC5000
can issue one instruction per class per pipeline clock cycle. Note that
this broad separation of classes insures that there are no data depen-
dencies to restrict multi-issue.
However, long-latency resources in either the floating-point ALU (e.g.
DIV or SQRT instructions) or instructions in the integer unit (such as
multiply) can restrict the issue of instructions. Note that the R5000 does
not perform out-of-order or speculative execution; instead, the pipeline
slips until the required resource becomes available.
There are no alignment restrictions on dual-issue instruction pairs.
The RC5000 fetches two instructions from the cache per cycle. Thus, for
optimal performance, compilers should attempt to align branch targets
to allow dual-issue on the first target cycle, since the instruction cache
only performs aligned fetches.
Table 1 Integer Instruction Execution Speed
The RC5000’s short pipeline keeps the load and branch latencies
very low. The caches contain special logic that allows any combination
of loads and stores to execute in back-to-back cycles without requiring
pipeline slips or stalls. (This assumes that the operation does not miss
in the cache.)
2 of 15
April 10, 2001
79RC5000
I0
1I
2I
1R
2R
1A
2A
1D
2D
1W
2W
I1
1I
2I
1R
2R
1A
2A
1D
2D
1W
2W
I2
1I
2I
1R
2R
1A
2A
1D
2D
W
1
I3
1I
2I
1R
2R
1A
2A
1D
I4
1I
2I
1R
2R
1A
one cycle
Figure 1 R5000 Integer Pipeline Stages
Key to Figure
1I-1R
2I
2A-2D
1D
1D-2D
2R
2R
2R
2R
1A
1A-2A
1A
2A
1A
2W
Instruction cache access
Instruction virtual to physical address translation
Data cache access and load align
Data virtual to physical address translation
Virtual to physical address translation
Register file read
Bypass calculation
Instruction decode
Branch address calculation
Issue or slip decision
Integer add, logical, shift
Data virtual address calculation
Store align
Branch decision
Register file write
3 of 15
April 10, 2001
79RC5000
RC5000 Computational Units
The RC5000 contains the following computational units:
Integer ALU. The RC5000 implements a full, single-cycle 64-bit ALU
for all integer ALU functions other than multiply and divide. Bypassing is
used to support back-to-back ALU operations at the full pipeline rate,
without requiring stalls for data dependencies.
Integer Multiply/Divide Unit. This unit is separated from the primary
ALU, to allow these longer latency operations to run in parallel with other
operations. The pipeline stalls only if an attempt to access the HI or LO
registers is made before the operation completes.
Floating-point ALU. This unit is responsible for all CP1/CP1X ALU
operations other than DIV/SQRT. The unit is pipelined to allow a single-
cycle repeat rate for single-precision operations
Floating-point DIV/SQRT unit. This unit is separated from the other
floating-point ALU, so that these long latency operations do not prevent
the issue of other floating point operations.
In addition, the RC5000 implements separate logical units to imple-
ment loads, stores, and branches.
Operating Frequency
The input clock operates in a frequency range of 33MHz to 100MHz.
The pipeline frequency for the RC5000 is 2 to 8 times the input clock (up
to the maximum for the speed grade of CPU).
where P is the maximum power consumption at hot temperature,
calculated by using the maximum I
CC
specification for the device.
Typical values for
∅
CA
at various airflows are shown in Table 1.
∅
CA
Airflow (ft/min)
PGA
BGA
0
16
14
200
7
6
400
5
4
600
3
3
800
2.5
2.5
1000
2
2
Table 2 Thermal Resistance (½CA) at Various Airflows
Note:
The RC5000 implements advanced power manage-
ment to substantially reduce the average power dissipation of
the device. This operation is described in the
IDT79RV5000
RISC Microprocessor Reference Manual.
Note:
Per the RC5000 Documentation errata, Revision 1.0, dated February
1999 and per the RC5000 Device errata, dated February 1999, mode
bits 20, 33 and 37 must be set to 1.
Revision History
January 1996:
Corrected pin list for Clock/Control, Initialization, and
Secondary Cache interfaces in Pin Description section. Changed pins
AA19 and AA21 from Vcc to Vss in Advance Pin-Out section.
March 1997:
Upgraded data sheet status from “Preliminary” to Final.
Added section on thermal considerations. Added section on absolute
maximum ratings.
June 1997:
Revised Power Consumption and System Interface
Parameters.
September 1997:
Added user notation on Boot Mode Bits 20 and 33
for 200 MHz frequency.
June 1998:
Added 250 MHz. Changed naming conventions.
June 1999:
Added 267 MHz and 300 MHz.
October 28, 1999:
Added industrial temperature data and revised
package designation code in the Ordering Information section.
March 23, 2000:
Expanded the data presentation in the System
Interface Parameters table and revised the values in this table.
April 10, 2001:
In the Data Output and Data Output Hold categories
of the System Interface Parameters table, changed values in the Min
column for all speeds from 1.5 and 1.0 to 0.
Thermal Considerations
The RC5000 utilizes special packaging techniques, to improve the
thermal properties of high-speed processors. The RC5000 is packaged
using cavity down packaging in a 223-pin PGA package with integral
thermal slug, and a 272-pin BGA package. These packages effectively
dissipate the power of the CPU, increasing device reliability.
The RC5000 utilizes an all-aluminum package with the die attached
to a normal copper lead frame mounted to the aluminum casing. Due to
the heat-spreading effect of the aluminum, the package allows for an
efficient thermal transfer between the die and the case. The aluminum
offers less internal resistance from one end of the package to the other,
reducing the temperature gradient across the package and therefore
presenting a greater area for convection and conduction to the PCB for
a given temperature. Even nominal amounts of airflow will dramatically
reduce the junction temperature of the die, resulting in cooler operation.
The RC5000 is guaranteed in a case temperature range of 0° to
+85° C. The type of package, speed (power) of the device, and airflow
conditions affect the equivalent ambient temperature conditions that will
meet this specification.
The equivalent allowable ambient temperature, T
A
, can be calculated
using the thermal resistance from case to ambient (∅
CA
) of the given
package.
The following equation relates ambient and case temperatures:
T
A
= T
C
- P *
∅
CA
4 of 15
April 10, 2001
79RC5000
Logic Diagram
SysAD(63:0)
SysADC(7:0)
SysCmd(8:0)
SysCmdP
System Interface
ValidIn*
ValidOut*
ExtRqst*
Release*
RdRdy*
WrRdy*
64
8
9
2
ScWord (1:0)
ScTCE*
ScTDE*
ScTOE*
ScCLR*
ScDCE*
ScDOE*
ScCWE*
ScLine (15:0)
ScMATCH
ScVALID
Secondary Cache Interface
JTAG
Interface
Initialization
Interface
Interrupt
Interface
16
SysClock
Clock Interface
VccP
VssP
Vcc
Vss
34
34
RC5000
Logic
Symbol
6
Int (5:0)*
NMI*
BigEndian
ModeClock
ModeIN
VccOk
ColdReset*
Reset*
JTDI
JTDO
JTMS
JTCK
Figure 2 RC5000 Logic Symbol Diagram
5 of 15
April 10, 2001
京公网安备 11010802033920号
EEWORLD
