3822 Group (A ver.)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0076-0120Z
Rev.1.20
2003.12.24
●LCD
drive control circuit
Bias ................................................................................... 1/2, 1/3
Duty ........................................................................... 1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output ........................................................................ 32
●2
clock generating circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power
source voltage
In high-speed mode
(at f(X
IN
)
≤
10 MHz) ................................................... 4.5 to 5.5 V
(at f(X
IN
)
≤
8 MHz) ..................................................... 4.0 to 5.5 V
In middle-speed mode (at f(X
IN
)
≤
6 MHz) ............... 1.8 to 5.5 V
In low-speed mode .................................................... 1.8 to 5.5 V
●Power
dissipation
In high-speed mode ................................................ 15 mW (std.)
(at f(X
IN
) = 8 MHz, Vcc = 5 V, Ta = 25 °C)
In low-speed mode ................................................... 24
µW
(std.)
(at f(X
IN
) stopped, f(X
CIN
) = 32 kHz, Vcc = 3 V, Ta = 25 °C)
●Operating
temperature range .................................. – 20 to 85 °C
DESCRIPTION
The 3822 group (A version) is the 8-bit microcomputer based on
the 740 family core technology.
The 3822 group (A version) has the LCD drive control circuit, an 8-
channel A-D converter, and a serial I/O as additional functions.
The various microcomputers in the 3822 group (A version) include
variations of internal memory size and packaging. For details, re-
fer to the section on part numbering.
FEATURES
●Basic
machine-language instructions ...................................... 71
●The
minimum instruction execution time ........................... 0.4 µs
(at f(X
IN
) = 10 MHz, High-speed mode)
●Memory
size
ROM ............................................................... 16 K to 48 K bytes
RAM ................................................................. 512 to 1024 bytes
●Programmable
input/output ports ............................................ 49
●Software
pull-up/pull-down resistors (Ports P0-P7 except port P4
0
)
●Interrupts
................................................. 17 sources, 16 vectors
(includes key input interrupt)
●Timers
........................................................... 8-bit
✕
3, 16-bit
✕
2
●Serial
I/O ...................... 8-bit
✕
1 (UART or Clock-synchronized)
●A-D
converter ................................................. 8-bit
✕
8 channels
APPLICATIONS
Camera, household appliances, consumer electronics, etc.
PIN CONFIGURATION (TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SEG
7
SEG
6
SEG
5
SEG
4
SEG
3
SEG
2
SEG
1
SEG
0
V
CC
V
REF
AV
SS
COM
3
COM
2
COM
1
COM
0
VL
3
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SEG
8
SEG
9
SEG
10
SEG
11
P3
4
/SEG
12
P3
5
/SEG
13
P3
6
/SEG
14
P3
7
/SEG
15
P0
0
/SEG
16
P0
1
/SEG
17
P0
2
/SEG
18
P0
3
/SEG
19
P0
4
/SEG
20
P0
5
/SEG
21
P0
6
/SEG
22
P0
7
/SEG
23
P1
0
/SEG
24
P1
1
/SEG
25
P1
2
/SEG
26
P1
3
/SEG
27
P1
4
/SEG
28
P1
5
/SEG
29
P1
6
/SEG
30
P1
7
/SEG
31
40
39
38
37
36
35
34
M3822XMXA-XXXFP
33
32
31
30
29
28
27
26
25
P2
0
P2
1
P2
2
P2
3
P2
4
P2
5
P2
6
P2
7
V
SS
X
OUT
X
IN
P7
0
/X
COUT
P7
1
/X
CIN
RESET
P4
0
P4
1
/φ
Package type : 80P6N-A (80-pin plastic-molded QFP)
Fig. 1 M3822XMXA-XXXFP pin configuration
Rev.1.20
Dec 24, 2003
page 1 of 57
VL
2
VL
1
P6
7
/AN
7
P6
6
/AN
6
P6
5
/AN
5
P6
4
/AN
4
P6
3
/AN
3
P6
2
/AN
2
P6
1
/AN
1
P6
0
/AN
0
P5
7
/ADT
P5
6
/T
OUT
P5
5
/CNTR
1
P5
4
/CNTR
0
P5
3
/RTP
1
P5
2
/RTP
0
P5
1
/INT
3
P5
0
/INT
2
P4
7
/S
RDY
P4
6
/S
CLK
P4
5
/T
X
D
P4
4
/R
X
D
P4
3
/INT
1
P4
2
/INT
0
3822 Group (A ver.)
PIN CONFIGURATION (TOP VIEW)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG
10
SEG
11
P3
4
/SEG
12
P3
5
/SEG
13
P3
6
/SEG
14
P3
7
/SEG
15
P0
0
/SEG
16
P0
1
/SEG
17
P0
2
/SEG
18
P0
3
/SEG
19
P0
4
/SEG
20
P0
5
/SEG
21
P0
6
/SEG
22
P0
7
/SEG
23
P1
0
/SEG
24
P1
1
/SEG
25
P1
2
/SEG
26
P1
3
/SEG
27
P1
4
/SEG
28
P1
5
/SEG
29
SEG
9
SEG
8
SEG
7
SEG
6
SEG
5
SEG
4
SEG
3
SEG
2
SEG
1
SEG
0
V
CC
V
REF
AV
SS
COM
3
COM
2
COM
1
COM
0
V
L3
V
L2
V
L1
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
19
20
7
8
9
10
11
12
13
14
15
16
17
18
3
4
1
2
5
6
40
39
38
37
36
35
34
33
32
M3822XMXA-XXXHP
31
30
29
28
27
26
25
24
23
22
21
P1
6
/SEG
30
P1
7
/SEG
31
P2
0
P2
1
P2
2
P2
3
P2
4
P2
5
P2
6
P2
7
V
SS
X
OUT
X
IN
P7
0
/X
COUT
P7
1
/X
CIN
RESET
P4
0
P4
1
/φ
P4
2
/INT
0
P4
3
/INT
1
Fig. 2 M3822XMXA-XXXHP pin configuration
Rev.1.20
Dec 24, 2003
page 2 of 57
P6
7
/AN
7
P6
6
/AN
6
P6
5
/AN
5
P6
4
/AN
4
P6
3
/AN
3
P6
2
/AN
2
P6
1
/AN
1
P6
0
/AN
0
P5
7
/ADT
P5
6
/T
OUT
P5
5
/CNTR
1
P5
4
/CNTR
0
P5
3
/RTP
1
P5
2
/RTP
0
P5
1
/INT
3
P5
0
/INT
2
P4
7
/S
RDY
P4
6
/S
CLK
P4
5
/T
X
D
P4
4
/R
X
D
Package type : 80P6Q-A
(80-pin plastic-molded QFP)
X
COUT
RTP
0
,RTP
1
P5(8)
P4(8)
X
CIN
Real time port function
φ
ADT
INT
2
,INT
3
INT
0
,INT
1
26 27
1
2
3 4
5
6
7
8
72 73
9 10 11 12 13 14 15 16
17 18 19 20 21 22 23 24
55 56 57 58
Key on wake up
Rev.1.20
Reset Input
RESET
(0V)
V
SS
30
25
71
3822 Group (A ver.)
FUNCTIONAL BLOCK DIAGRAM (Package type : 80P6Q-A)
Fig. 3 Functional block diagram
Dec 24, 2003
(5V)
V
CC
Main Clock Main Clock
Output X
OUT
Input X
IN
28
29
page 3 of 57
Data bus
C P U
A
ROM
X
Y
S
PC
H
PC
L
Timer X(16)
Timer Y(16)
Timer 1(8)
Timer 3(8)
Timer 2(8)
PS
LCD display
RAM
(16 bytes)
RAM
80
79
77
Clock generating
circuit
V
L 1
V
L 2
78
V
L3
LCD
drive control
circuit
76
X
CIN
X
COUT
φ
Sub-Clock Sub-Clock
Input
Output
COM
0
COM
1
75
COM
2
74
COM
3
70
69
SEG
0
SEG
1
68
SEG
2
67
SEG
3
66
SEG
4
65
SEG
5
64
SEG
6
63
SEG
7
62
SEG
8
61
SEG
9
60
SEG
10
59
SEG
11
A-D
converter(8)
SI/O(8)
T
OUT
CNTR
0
,CNTR
1
P7(2)
P6(8)
P3(4)
P2(8)
P1(8)
P0(8)
31 32 33 34 35 36 37 38
39 40 41 42 43 44 45 46
47 48 49 50 51 52 53 54
I/O Port P7
I/O Port P6
I/O Port P5
V
REF
AV
SS
(0V)
I/O Port P4
Input Port P3
I/O Port P2
I/O Port P1
I/O Port P0
3822 Group (A ver.)
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
V
CC
, V
SS
V
REF
AV
SS
Name
Power source
Analog refer-
ence voltage
Analog power
source
Reset input
Clock input
Clock output
Function
Function except a port function
•Apply voltage of power source to V
CC
, and 0 V to V
SS
. (For the limits of V
CC
, refer to “Recom-
mended operating conditions”).
•Reference voltage input pin for A-D converter.
•GND input pin for A-D converter.
•Connect to V
SS
.
•Reset input pin for active “L”.
•Input and output pins for the main clock generating circuit.
•Feedback resistor is built in between X
IN
pin and X
OUT
pin.
•Connect a ceramic resonator or a quartz-crystal oscillator between the X
IN
and X
OUT
pins to set
the oscillation frequency.
•If an external clock is used, connect the clock source to the X
IN
pin and leave the X
OUT
pin open.
•This clock is used as the oscillating source of system clock.
RESET
X
IN
X
OUT
V
L1
–V
L3
COM
0
–COM
3
LCD power
source
Common output
•Input 0
≤
V
L1
≤
V
L2
≤
V
L3
≤
V
CC
voltage.
•Input 0 – V
L3
voltage to LCD.
•LCD common output pins.
•COM
2
and COM
3
are not used at 1/2 duty ratio.
•COM
3
is not used at 1/3 duty ratio.
SEG
0
–SEG
11
P0
0
/SEG
16
–
P0
7
/SEG
23
Segment output
I/O port P0
•LCD segment output pins.
•8-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•LCD segment output pins
P1
0
/SEG
24
–
P1
7
/SEG
31
P2
0
– P2
7
I/O port P1
•I/O direction register allows each port to be individually
programmed as either input or output.
•Pull-down control is enabled.
•8-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•Key input (key-on wake-up) interrupt
input pins
I/O port P2
P3
4
/SEG
12
–
P3
7
/SEG
15
Input port P3
•4-bit input port.
•CMOS compatible input level.
•Pull-down control is enabled.
•LCD segment output pins
Rev.1.20
Dec 24, 2003
page 4 of 57
3822 Group (A ver.)
Table 2 Pin description (2)
Pin
P4
0
P4
1
/φ
P4
2
/INT
0
,
P4
3
/INT
1
P4
4
/R
X
D,
P4
5
/T
X
D,
P4
6
/S
CLK
,
P4
7
/S
RDY
P5
0
/INT
2
,
P5
1
/INT
3
P5
2
/RTP
0
,
P5
3
/RTP
1
P5
4
/CNTR
0
,
P5
5
/CNTR
1
P5
6
/T
OUT
P5
7
/ADT
P6
0
/AN
0
–
P6
7
/AN
7
I/O port P6
•8-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
P7
0
/X
COUT,
P7
1
/X
CIN
I/O port P7
•2-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•Sub-clock generating circuit I/O pins.
(Connect a resonator. External clock
cannot be used.)
Name
Input port P4
I/O port P4
•1-bit Input port.
•CMOS compatible input level.
•7-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
I/O port P5
•8-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•Real time port function pins
•Timer X, Y function pins
•Timer 2 output pins
•A-D trigger input pins
•A-D conversion input pins
•Interrupt input pins
•Serial I/O function pins
•φ clock output pin
•Interrupt input pins
Function
Function except a port function
Rev.1.20
Dec 24, 2003
page 5 of 57
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