Keep safety first in your circuit designs!
•
Renesas Technology Corporation puts the maximum effort into making semiconductor prod-
ucts better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with ap-
propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
• These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corporation product best suited to the customer's application; they do
not convey any license under any intellectual property rights, or any other rights, belonging
to Renesas Technology Corporation or a third party.
• Renesas Technology Corporation assumes no responsibility for any damage, or infringe-
ment of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
• All information contained in these materials, including product data, diagrams, charts, pro-
grams and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corporation without notice
due to product improvements or other reasons. It is therefore recommended that custom-
ers contact Renesas Technology Corporation or an authorized Renesas Technology Cor-
poration product distributor for the latest product information before purchasing a product
listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or
other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by
various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
• When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs, and algorithms, please be sure to evaluate all informa-
tion as a total system before making a final decision on the applicability of the information
and products. Renesas Technology Corporation assumes no responsibility for any dam-
age, liability or other loss resulting from the information contained herein.
• Renesas Technology Corporation semiconductors are not designed or manufactured for
use in a device or system that is used under circumstances in which human life is poten-
tially at stake. Please contact Renesas Technology Corporation or an authorized Renesas
Technology Corporation product distributor when considering the use of a product con-
tained herein for any specific purposes, such as apparatus or systems for transportation,
vehicular, medical, aerospace, nuclear, or undersea repeater use.
• The prior written approval of Renesas Technology Corporation is necessary to reprint or
reproduce in whole or in part these materials.
• If these products or technologies are subject to the Japanese export control restrictions,
they must be exported under a license from the Japanese government and cannot be im-
ported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/
or the country of destination is prohibited.
• Please contact Renesas Technology Corporation for further details on these materials or t
he products contained therein.
REVISION HISTORY
Rev.
Date
Page
1.0
Aug. 30, 2001
–
First edition issued
3850 Group (Spec. H) User’s Manual
Description
Summary
1.1
Sep. 10, 2001
3-5
1.02
Aug. 29, 2003
1-6
1-7
1-7
1-37
1-38
2-103
2-104
2-105
2-106
2-107
3-4
3-20
3-22
3-24
1.03
Sep. 18, 2003
1-51
Limits and test conditions into Table 3.1.5 are partly added.
Fig. 4 is partly revised.
Table 2 is partly added.
Note of Table 3 is added.
Fig. 42 is partly revised.
Fig. 43 is partly revised.
Clause name of “2.11 Flash memory mode” is revised.
Notes of Fig. 2.11.3 are partly revised.
Table 2.11.2 is partly revised.
Explanations of “[Beginning procedure]” of “2.11.6 CPU rewrite mode” are partly
added.
Explanations of this page are added.
Parameter of Table 3.1.4 is partly revised.
Fig. 3.2.16 is partly revised.
Fig. 3.2.20 is partly revised.
Fig. 3.2.24 is partly revised.
Fig. 52 is partly revised.
(1/1)
Analog electronics
京公网安备 11010802033920号
EEWORLD
