3882 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
REJ03B0089-0101
Rev.1.01
Nov 14, 2005
GENERAL DESCRIPTION
The 3882 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 3882 group is designed for Keyboard Controller for the note
book PC.
FEATURES
<Microcomputer mode>
qBasic
machine-language instructions ...................................... 71
qMinimum
instruction execution time .................................. 0.5
µs
(at 8 MHz oscillation frequency)
qMemory
size
ROM ............................................................................. 20K bytes
RAM ............................................................................ 1024 bytes
qProgrammable
input/output ports ............................................ 72
qSoftware
pull-up transistors ....................................................... 8
qInterrupts
................................................. 17 sources, 14 vectors
qTimers
............................................................................. 8-bit
✕
4
qWatchdog
timer ............................................................ 16-bit
✕
1
qLPC
interface .............................................................. 2 channels
qSerialized
IRQ ................................................................ 3 factors
qClock
generating circuit ..................................... Built-in 1 circuits
(connect to external ceramic resonator)
qPower
source voltage ................................................ 3.0 to 3.6 V
qPower
dissipation
In high-speed mode .......................................................... 20 mW
(at 8 MHz oscillation frequency, at 3.3 V power source voltage)
qOperating
temperature range .................................... –20 to 85°C
APPLICATION
Note book PC
PIN CONFIGURATION (TOP VIEW)
48
47
46
45
60
59
58
44
43
51
50
49
57
56
55
54
53
52
42
41
40
39
38
37
36
35
34
33
P3
2
P3
3
P3
4
P3
5
P3
6
P3
7
P0
0
P0
1
P0
2
P0
3
P0
4
P0
5
P0
6
P0
7
P1
0
P1
1
P1
2
P1
3
P1
4
P1
5
P3
1
P3
0
P8
7
/SERIRQ
P8
6
/LCLK
P8
5
/LRESET
P8
4
/LFRAME
P8
3
/LAD
3
P8
2
/LAD
2
P8
1
/LAD
1
P8
0
/LAD
0
V
CC
NC
NC
P6
7
P6
6
P6
5
P6
4
P6
3
P6
2
P6
1
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
M38827G5-XXXHP
M38827G5HP
32
31
30
29
28
27
26
25
24
23
22
21
P1
6
P1
7
P2
0
P2
1
P2
2
P2
3
P2
4
(LED
0
)
P2
5
(LED
1
)
P2
6
(LED
2
)
P2
7
(LED
3
)
V
SS
X
OUT
X
IN
P4
0
P4
1
RESET
CNV
SS
P4
2
/INT
0
P4
3
/INT
1
P4
4
13
14
15
16
17
12
11
Package type : PLQP0080KB-A (80P6Q-A)
Fig. 1 Pin configuration
Rev.1.01 Nov 14, 2005
REJ03B0089-0101
page 1 of 60
P6
0
P7
7
P7
6
P7
5
/INT
41
P7
4
/INT
31
P7
3
/INT
21
P7
2
P7
1
P7
0
P5
7
P5
6
P5
5
/CNTR
1
P5
4
/CNTR
0
P5
3
/INT
40
P5
2
/INT
30
P5
1
/INT
20
P5
0
/INT
5
P4
7
/CLKRUN
P4
6
P4
5
10
18
19
20
6
3
4
5
7
8
1
2
9
FUNCTIONAL BLOCK DIAGRAM (Package : PLQP0080KB-A)
Reset input
V
SS
V
CC
RESET
25
24
71
30
3882 Group
Main-clock
input
X
IN
CNV
SS
Main-clock
output
X
OUT
Rev.1.01 Nov 14, 2005
REJ03B0089-0101
C P U
Fig. 2 Functional block diagram
A
X
Prescaler 12 (8)
Prescaler X (8)
28
29
Clock generating circuit
page 2 of 60
RAM
ROM
Y
Timer 1 (8)
Timer 2 (8)
Timer X (8)
Timer Y (8)
S
PC
H
Prescaler Y (8)
PC
L
PS
CNTR
0
CNTR
1
Watchdog
timer
Reset
CLKRUN
INT
20,
INT
30,
INT
40,
INT
5
INT
0,
INT
1
LPC interface
INT
21,
INT
31,
INT
41
Key-on
wake-up
P8(8)
P6(8)
P5(8)
P7(8)
P4(8)
P3(8)
P2(8)
P1(8)
P0(8)
63 64 65 66 67 68 69 70
2 3 4 5 6 7 8 9
72 73
74 75 76 77 78 79 80 1
10 11 12 13 14 15 16 17
18 19 20 21 22 23 26 27
55 56 57 58 59 60 61 62
31 32 33 34 35 36 37 38
39 40 41 42 43 44 45 46
47 48 49 50 51 52 53 54
NC
NC
I/O port P8
I/O port P6
I/O port P7
I/O port P5
I/O port P4
I/O port P3
I/O port P2
I/O port P1
I/O port P0
3882 Group
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
V
CC
, V
SS
CNV
SS
RESET
X
IN
X
OUT
Name
Power source
CNV
SS
input
Reset input
Clock input
Clock output
Functions
•Apply voltage of 3.3 V ±10 % to Vcc, and 0 V to Vss.
•Connected to V
SS
.
•Reset input pin for active “L”.
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator between the X
IN
and X
OUT
pins to set the oscillation frequency.
•When an external clock is used, connect the clock source to the X
IN
pin and leave the X
OUT
pin open.
•8-bit I/O port.
P0
0
–P0
7
I/O port P0
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure or N-channel open-drain output structure.
•8-bit I/O port.
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level.
•CMOS 3-state output structure or N-channel open-drain output structure.
•8-bit I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
P2
0
–P2
7
I/O port P2
•CMOS compatible input level.
•CMOS 3-state output structure.
•P2
4
to P2
7
(4 bits) are enabled to output large current for LED drive.
•8-bit I/O port.
•I/O direction register allows each pin to be individually
programmed as either input or output.
P3
0
–P3
7
I/O port P3
•CMOS compatible input level.
•CMOS 3-state output structure.
•These pins function as key-on wake-up .
•These pins are enabled to control pull-up.
•Key-on wake-up input pins
Function except a port function
P1
0
–P1
7
I/O port P1
Rev.1.01 Nov 14, 2005
REJ03B0089-0101
page 3 of 60
3882 Group
Table 2 Pin description (2)
Pin
P4
0
P4
1
P4
2
/INT
0
P4
3
/INT
1
P4
4
P4
5
P4
6
P4
7
/CLKRUN
P5
0
/INT
5
P5
1
/INT
20
P5
2
/INT
30
P5
3
/INT
40
P5
4
/CNTR
0
P5
5
/CNTR
1
P5
6
P5
7
•8-bit I/O port with the same function as port P0
P6
0
–P6
7
P7
0
P7
1
P7
2
P7
3
/INT
21
P7
4
/INT
31
P7
5
/INT
41
P7
6
P7
7
P8
0
/LAD
0
P8
1
/LAD
1
P8
2
/LAD
2
P8
3
/LAD
3
P8
4
/LFRAME
P8
5
/LRESET
P8
6
/LCLK
P8
7
/SERIRQ
•Serialized IRQ function pin
I/O port P6
•CMOS compatible input level.
•CMOS 3-state output structure.
•8-bit CMOS I/O port with the same function as port P0
<Input level>
P7
0
–P7
5
: CMOS compatible input level or
TTL compatible input level
I/O port P7
P7
6
, P7
7
: CMOS compatible input level
<Output structure>
N-channel open-drain output structure
•Each pin level of P7
0
to P7
5
can be read even in
output port mode.
•8-bit CMOS I/O port with the same function as port
P0
•CMOS compatible input level.
•CMOS 3-state output structure.
I/O port P8
•LPC interface function pins
•Interrupt input pins
I/O port P4
Name
Functions
•8-bit I/O port with the same function as port P0
<Input level>
CMOS compatible input level
<Output level>
P4
0
, P4
1
: CMOS 3-state output structure
P4
2
-P4
7
: CMOS 3-state output structure or N-
channel open-drain output structure
•Each pin level of P4
2
to P4
6
can be read even in
output port mode.
•8-bit I/O port with the same function as port P0
•CMOS compatible input level
•CMOS 3-state output structure
I/O port P5
•Timer X, timer Y function pins
•Interrupt input pins
•Serialized IRQ function pin
•Interrupt input pins
Function except a port function
Rev.1.01 Nov 14, 2005
REJ03B0089-0101
page 4 of 60
3882 Group
PART NUMBERING
Product name
M3882
7
G
5
-XXX
HP
Package type
HP : PLQP0080KB-A
ROM number
Omitted in in shipped in blank version.
ROM size
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
9: 36864 bytes
A: 40960 bytes
B: 45056 bytes
C: 49152 bytes
D: 53248 bytes
E: 57344 bytes
F: 61440 bytes
7 : 28672 bytes
8 : 32768 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved
areas ; user cannot use those bytes.
However, they can be programmed or erased in the flash
memory version, so that the users can use them.
Memory type
M : Mask ROM version
F : Flash memory version
G : QzROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Fig. 3 Part numbering
Rev.1.01 Nov 14, 2005
REJ03B0089-0101
page 5 of 60
Embedded System
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