Philips Semiconductors
Product specification
P-channel enhancement mode
MOS transistor
FEATURES
• Low threshold voltage
• Fast switching
• Logic level compatible
• Subminiature surface mount
package
BSH202
SYMBOL
s
QUICK REFERENCE DATA
V
DS
= -30 V
I
D
= -0.52 A
R
DS(ON)
≤
0.9
Ω
(V
GS
= -10 V)
d
g
GENERAL DESCRIPTION
P-channel, enhancement mode,
logic level, field-effect power
transistor. This device has low
threshold voltage and extremely
fast switching making it ideal for
battery powered applications and
high speed digital interfacing.
The BSH202 is supplied in the
SOT23
subminiature
surface
mounting package.
PINNING
PIN
1
2
3
gate
source
drain
DESCRIPTION
SOT23
3
Top view
1
2
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
R
GS
= 20 kΩ
T
a
= 25 ˚C
T
a
= 100 ˚C
T
a
= 25 ˚C
T
a
= 25 ˚C
T
a
= 100 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
-30
-30
±
20
-0.52
-0.33
-2.1
0.417
0.17
150
UNIT
V
V
V
A
A
A
W
W
˚C
THERMAL RESISTANCES
SYMBOL
R
th j-a
PARAMETER
Thermal resistance junction to
ambient
CONDITIONS
FR4 board, minimum
footprint
TYP.
300
MAX.
-
UNIT
K/W
August 1998
1
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode
MOS transistor
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER
V
(BR)DSS
V
GS(TO)
R
DS(ON)
g
fs
I
GSS
I
DSS
Q
g(tot)
Q
gs
Q
gd
t
d on
t
r
t
d off
t
f
C
iss
C
oss
C
rss
Drain-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
CONDITIONS
V
GS
= 0 V; I
D
= -10
µA
V
DS
= V
GS
; I
D
= -1 mA
T
j
= 150˚C
V
GS
= -10 V; I
D
= -280 mA
V
GS
= -4.5 V; I
D
= -140 mA
V
GS
= -10 V; I
D
= -280 mA; T
j
= 150˚C
Forward transconductance
V
DS
= -24 V; I
D
= -280 mA
Gate source leakage current V
GS
=
±20
V; V
DS
= 0 V
Zero gate voltage drain
V
DS
= -24 V; V
GS
= 0 V;
current
T
j
= 150˚C
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
Input capacitance
Output capacitance
Feedback capacitance
I
D
= -0.3 A; V
DD
= -15 V; V
GS
= -10 V
MIN.
-30
-1
-0.4
-
-
-
0.2
-
-
-
-
-
-
-
-
-
-
-
-
-
BSH202
TYP. MAX. UNIT
-
-1.9
-
0.63
0.89
0.95
0.7
±10
-50
-0.4
2.9
0.4
0.5
2
4.5
45
20
80
27
9
-
-
-
0.9
1.35
1.35
-
±100
-100
-10
-
-
-
-
-
-
-
-
-
-
V
V
V
Ω
Ω
Ω
S
nA
nA
µA
nC
nC
nC
ns
ns
ns
ns
pF
pF
pF
V
DD
= -15 V; I
D
= -0.5 A;
V
GS
= -10 V; R
G
= 6
Ω
Resistive load
V
GS
= 0 V; V
DS
= -24 V; f = 1 MHz
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL
I
DR
I
DRM
V
SD
t
rr
Q
rr
PARAMETER
Continuous reverse drain
current
Pulsed reverse drain current
Diode forward voltage
Reverse recovery time
Reverse recovery charge
CONDITIONS
T
a
= 25 ˚C
I
F
= -0.5 A; V
GS
= 0 V
I
F
= -0.5 A; -dI
F
/dt = 100 A/µs;
V
GS
= 0 V; V
R
= -24 V
MIN.
-
-
-
-
-
TYP.
-
-
-0.87
30
28
MAX.
-0.56
-2.2
-1.3
-
-
UNIT
A
A
V
ns
nC
August 1998
2
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode
MOS transistor
BSH202
Normalised Power Dissipation, PD (%)
120
100
100
80
60
40
1
20
10
1000
Peak Pulsed Drain Current, IDM (A)
D = 0.5
0.2
0.1
0.05
0.02
single pulse
P
D
tp
D = tp/T
T
0
0
25
50
75
100
125
150
Ambient Temperature, Ta (C)
0.1
1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00 1E+01
Pulse width, tp (s)
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
a
)
Fig.4. Transient thermal impedance.
Z
th j-a
= f(t); parameter D = t
p
/T
Normalised Drain Current, ID (%)
120
100
80
60
40
20
Drain current, ID (A)
-1.4
Tj = 25 C
-1.2
-1
VGS = -10 V
-4.5 V
BSH202
-3.5 V
-3.3 V
-0.8
-0.6
-0.4
-0.2
-3.1 V
-2.9 V
-2.7 V
-2.5 V
0
0
25
50
75
100
125
150
0
0
-0.5
-1
-1.5
Drain-Source Voltage, VDS (V)
-2
Ambient Temperature, Ta (C)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
a
); conditions: V
GS
≤
-10 V
Fig.5. Typical output characteristics, T
j
= 25 ˚C.
I
D
= f(V
DS
); parameter V
GS
Drain-Source On Resistance, RDS(on) (Ohms)
10
Peak Pulsed Drain Current, IDM (A)
BSH202
tp = 10us
1
RDS(on) = VDS/ ID
100 us
1 ms
10 ms
0.1
d.c.
0.01
100 ms
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
-2.5 V -2.7 V -2.9 V
-3.1 V
-3.3 V
-3.5 V
BSH202
Tj = 25 C
-4.5 V
VGS = -10 V
0.001
0.1
1
10
Drain-Source Voltage, VDS (V)
100
-0.2
-0.4
-0.6
-0.8
Drain Current, ID (A)
-1
-1.2
-1.4
Fig.3. Safe operating area. T
a
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.6. Typical on-state resistance, T
j
= 25 ˚C.
R
DS(ON)
= f(I
D
); parameter V
GS
August 1998
3
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode
MOS transistor
BSH202
Drain Current, ID (A)
-2
-1.8
-1.6
-1.4
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
0
-0.5
-1
-1.5 -2 -2.5 -3 -3.5 -4
Gate-Source Voltage, VGS (V)
-4.5
VDS > ID X RDS(on)
Tj = 25 C
150 C
BSH202
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Threshold Voltage, VGS(to), (V)
typical
minimum
0
-5
-5.5
25
50
75
100
125
150
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
)
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
Transconductance, gfs (S)
1.4
VDS > ID X RDS(on)
1.2
1
0.8
0.6
0.4
0.2
0
Tj = 25 C
BSH202
1E-01
1E-02
150 C
1E-03
1E-04
1E-05
1E-06
Drain Current, ID (A)
VDS = -5 V
Tj = 25 C
BSH202
0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 -1.1 -1.2 -1.3 -1.4
Drain Current, ID (A)
1E-07
-2.5
-2
-1.5
Gate-Source Voltage, VGS (V)
-1
Fig.8. Typical transconductance, T
j
= 25 ˚C.
g
fs
= f(I
D
)
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C
Normalised Drain-Source On Resistance
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0
RDS(ON) @ Tj
RDS(ON) @ 25C
VGS = -10 V
-4.5 V
Capacitances, Ciss, Coss, Crss (pF)
1000
BSH202
100
Ciss
Coss
10
Crss
25
50
75
100
125
150
Junction Temperature, Tj (C)
1
-0.1
-1.0
-10.0
Drain-Source Voltage, VDS (V)
-100.0
Fig.9. Normalised drain-source on-state resistance.
R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
)
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
August 1998
4
Rev 1.000
Philips Semiconductors
Product specification
P-channel enhancement mode
MOS transistor
BSH202
Gate-source voltage, VGS (V)
-14
-12
-10
-8
-6
-4
-2
0
0
1
2
Gate charge, (nC)
3
VDD = 15 V
RD = 50 Ohms
Tj = 25 C
BSH202
4
3.5
3
2.5
2
1.5
1
0.5
0
Source-Drain Diode Current, IF (A)
BSH202
150 C
Tj = 25 C
0
4
0.5
1
1.5
2
Drain-Source Voltage, VSDS (V)
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
)
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
August 1998
5
Rev 1.000
Embedded System
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