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PHP30NQ15T
N-channel TrenchMOS standard level FET
Rev. 03 — 3 March 2010
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Suitable for high frequency
applications due to fast switching
characteristics
1.3 Applications
DC-to-DC convertors
Switched-mode power supplies
1.4 Quick reference data
Table 1.
V
DS
I
D
P
tot
Quick reference
Conditions
T
mb
= 25 °C; V
GS
= 10 V;
see
Figure 1
and
2
T
mb
= 25 °C; see
Figure 3
Min
-
-
-
Typ
-
-
-
Max
150
29
150
Unit
V
A
W
drain-source voltage T
j
≥
25 °C; T
j
≤
175 °C
drain current
total power
dissipation
gate-drain charge
Symbol Parameter
Dynamic characteristics
Q
GD
V
GS
= 10 V; I
D
= 30 A;
V
DS
= 120 V; T
j
= 25 °C;
see
Figure 13
V
GS
= 10 V; I
D
= 15 A;
T
j
= 25 °C;
see
Figure 11
and
12
-
20
27
nC
Static characteristics
R
DSon
drain-source
on-state resistance
-
60
63
mΩ
NXP Semiconductors
PHP30NQ15T
N-channel TrenchMOS standard level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol
G
D
S
D
Description
gate
drain
source
mounting base; connected to
drain
mb
D
Simplified outline
Graphic symbol
G
mbb076
S
1 2 3
SOT78 (TO-220AB)
3. Ordering information
Table 3.
Ordering information
Package
Name
PHP30NQ15T
TO-220AB
Description
Version
plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead SOT78
TO-220AB
Type number
PHP30NQ15T_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 3 March 2010
2 of 13
NXP Semiconductors
PHP30NQ15T
N-channel TrenchMOS standard level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
T
mb
= 25 °C
t
p
≤
10 µs; pulsed; T
mb
= 25 °C
V
GS
= 10 V; T
mb
= 25 °C; see
Figure 1
and
2
V
GS
= 10 V; T
mb
= 100 °C; see
Figure 1
t
p
≤
10 µs; pulsed; T
mb
= 25 °C; see
Figure 2
T
mb
= 25 °C; see
Figure 3
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
j
≥
25 °C; T
j
≤
175 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-
-
-
Max
150
150
20
29
20
116
150
175
175
29
116
502
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
non-repetitive
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 26 A; V
sup
≤
25 V;
drain-source avalanche unclamped; R
GS
= 50
Ω;
t
p
= 0.2 ms; see
Figure 4
energy
non-repetitive
avalanche current
V
sup
≤
25 V; V
GS
= 10 V; T
j(init)
= 25 °C;
R
GS
= 50
Ω;
unclamped; see
Figure 4
I
AS
-
29
A
120
I
der
(%)
80
03aa24
003aaa055
10
3
I
D
(A)
10
2
t
p
= 10
μs
10
100
μs
1 ms
R
DSon
= V
DS
/ I
D
40
1
D.C.
10 ms
100 ms
0
0
50
100
150
T
mb
(°C)
200
10
−1
1
10
10
2
V
DS
(V)
10
3
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Safe operating area; continuous and peak drain
currents as a function of drain-source voltage
PHP30NQ15T_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 3 March 2010
3 of 13
NXP Semiconductors
PHP30NQ15T
N-channel TrenchMOS standard level FET
120
P
der
(%)
80
03aa16
10
2
003aaa054
I
AS
(A)
10
25
°C
T
j
prior to avalanche = 150
°C
40
1
0
0
50
100
150
T
mb
(°C)
200
10
−1
10
−3
10
−2
10
−1
1
t
p
(ms)
10
Fig 3.
Normalized total power dissipation as a
function of mounting base temperature
Fig 4.
Non-repetitive avalanche ruggedness current
as a function of pulse duration
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
Conditions
Min
-
Typ
-
Max
1
Unit
K/W
thermal resistance from see
Figure 5
junction to mounting
base
thermal resistance from vertical in still air
junction to ambient
R
th(j-a)
-
60
-
K/W
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
0.1
10
−1
0.05
0.02
P
10
−2
Single Pulse
003aaa056
δ
=
t
p
T
t
p
10
−3
10
−6
T
10
−5
10
−4
10
−3
10
−2
10
−1
t
p
(s)
t
1
Fig 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PHP30NQ15T_3
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 3 March 2010
4 of 13
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