INTEGRATED CIRCUITS
DATA SHEET
TZA3044; TZA3044B
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet
postamplifiers
Product specification
Supersedes data of 1999 Mar 16
File under Integrated Circuits, IC19
1999 Nov 03
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
FEATURES
•
Pin compatible with the NE/SA5224 and NE/SA5225 but
with extended power supply range and less external
component count
•
Wideband operation from 1.0 kHz to 1.25 GHz typical
•
Applicable in 622 Mbits/s SDH/SONET receivers and
1.25 Gbits/s Gigabit Ethernet receivers
•
Single supply voltage from 3.0 to 5.5 V
•
Positive Emitter Coupled Logic (PECL) compatible data
outputs
•
Positive Emitter Coupled Logic (PECL) compatible
status outputs (TTL compatible status outputs for the
TZA3044B)
•
Programmable input signal level detection to be
adjusted using a single external resistor
•
On-chip DC offset compensation without external
capacitor.
ORDERING INFORMATION
TYPE
NUMBER
TZA3044T
TZA3044TT
TZA3044U
TZA3044BT
TZA3044BTT
TZA3044BU
PACKAGE
NAME
SO16
TSSOP16
−
SO16
TSSOP16
−
DESCRIPTION
APPLICATIONS
TZA3044; TZA3044B
•
Digital fibre optic receiver for SDH/SONET STM4/OC12
and Gigabit Ethernet applications
•
Wideband RF gain block.
GENERAL DESCRIPTION
The TZA3044 is a high gain limiting amplifier that is
designed to process signals from fibre optic preamplifiers
like the TZA3043 and TZA3023. It is pin compatible with
the NE/SA5224 and NE/SA5225 but with extended power
supply range, and needs less external components.
Capable of operating up to 1.25 Gbits/s, the chip has input
signal level detection with a user-programmable threshold.
The data and level detection status outputs are differential
outputs for optimum noise margin and ease of use.
The TZA3044B has the same functionality as the
TZA3044, but with TTL compatible status outputs
(pins ST and STQ), and TTL compatible JAM input.
VERSION
SOT109-1
SOT403-1
−
SOT109-1
SOT403-1
−
plastic small outline package; 16 leads; body width 3.9 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
bare die in waffle pack carriers; die dimensions 1.55
×
1.55 mm
plastic small outline package; 16 leads; body width 3.9 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
bare die in waffle pack carriers; die dimensions 1.55
×
1.55 mm
1999 Nov 03
2
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
BLOCK DIAGRAM
TZA3044; TZA3044B
handbook, full pagewidth
TEST
2
(2, 10, 15, 21, 26)
DC-OFFSET
COMPENSATION
DIN
DINQ
4 (7)
5 (8)
A1
A2
A3
TZA3044
(24) 13
(23) 12
(16) 8
(18) 10
DOUT
DOUTQ
JAM
ST
STQ
25 kΩ
RECTIFIER
RSET
Vref
16 (30)
15 (29)
1 kΩ
A4
BAND GAP
REFERENCE
(17) 9
(3, 4, 6, 9)
3
AGND
(1, 14)
1
(11, 12)
6
VCCA
(13)
7
CF
(19, 20, 22, 25)
11
(27, 28)
14
MGR240
SUB
DGND
VCCD
The numbers in brackets refer to the pad numbers of the bare die version.
Fig.1 Block diagram.
handbook, halfpage
handbook, halfpage
SUB 1
TEST 2
AGND 3
DIN 4
DINQ 5
VCCA 6
CF 7
JAM 8
MGR241
16 RSET
15 Vref
14 VCCD
13 DOUT
TZA3044T
TZA3044BT
12 DOUTQ
11 DGND
10 ST
9
STQ
SUB 1
TEST 2
AGND 3
DIN 4
16 RSET
15 Vref
14 VCCD
TZA3044TT
13 DOUT
TZA3044BTT
12 DOUTQ
DINQ 5
VCCA 6
CF 7
JAM 8
MBK998
11 DGND
10 ST
9
STQ
Fig.2
Pin configuration of TZA3044T and
TZA3044BT.
Fig.3
Pin configuration of TZA3044TT and
TZA3044BTT.
1999 Nov 03
3
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
PINNING
PIN
SYMBOL TZA3044T
TZA3044TT
SUB
TEST
AGND
DIN
DINQ
V
CCA
CF
1
2
3
4
5
6
7
PAD
TZA3044U
1, 14
2, 10, 15,
21, 26
3, 4, 6, 9
7
8
11, 12
13
TYPE
(1)
S
−
S
I
I
S
A
TZA3044; TZA3044B
DESCRIPTION
substrate pin; must be at the same potential as pin AGND
for test purpose only; to be left open in the application
analog ground; must be at the same potential as pin DGND
differential input; complementary to pin DINQ; DC bias level is set
internally at approximately 2.1 V
differential input; complementary to pin DIN; DC bias level is set
internally at approximately 2.1 V
analog supply voltage; must be at the same potential as pin V
CCD
input for connection of capacitor to set time constant of level
detector input filter (optional); the capacitor should be connected
between V
CCA
and pin CF
PECL-compatible input (TTL compatible for the TZA3044B);
controls the output buffers pins DOUT and DOUTQ; when a LOW
signal is applied, the outputs will follow the input signal; when a
HIGH signal is applied, the output buffers will latch into LOW and
HIGH states respectively; when not connected, pin JAM is actively
pulled LOW
PECL-compatible status output of the input signal level detector
(TTL compatible for the TZA3044B); when the input signal is below
the user-programmed threshold level, this output is HIGH;
complementary to pin ST
PECL-compatible status output of the input signal level detector
(TTL compatible for the TZA3044B); when the input signal is below
the user-programmed threshold level, this output is LOW;
complementary to pin STQ
digital ground; must be at the same potential as pin AGND
PECL-compatible differential output; forced into a HIGH condition
when pin JAM is HIGH; complementary to pin DOUT
PECL-compatible differential output; forced into a LOW condition
when pin JAM is HIGH; complementary to pin DOUTQ
digital supply voltage; must be at the same potential as V
CCA
band gap reference voltage; typical value is 1.2 V; internal series
resistor of 1 kΩ
input signal level detector programming; nominal DC voltage is
V
CCA
−
1.5 V; threshold level is set by connecting an external
resistor between V
CCA
and pin RSET or by forcing a current into
pin RSET; default value for this resistor is 180 kΩ which
corresponds with approximately 4 mV (p-p) differential input signal
not connected
JAM
8
16
I
STQ
9
17
O
ST
10
18
O
DGND
DOUTQ
DOUT
V
CCD
V
ref
RSET
11
12
13
14
15
16
19, 20, 22,
25
23
24
27, 28
29
30
S
O
O
S
O
A
n.c.
Note
−
5, 31, 32
−
1. Pin type abbreviations: O = Output, I = Input, S = power Supply and A = Analog function.
1999 Nov 03
4
Philips Semiconductors
Product specification
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
FUNCTIONAL DESCRIPTION
The TZA3044 accepts up to 1.25 Gbits/s data streams,
with amplitudes from 2 mV (p-p) up to 1.5 V (p-p)
single-ended. The input signal will be amplified and limited
to differential PECL output levels (see Fig.1).
The input buffer A1 presents an impedance of
approximately 4.5 kΩ to the data stream on the inputs DIN
and DINQ. The input can be used both single-ended and
differential, but differential operation is preferred for better
performance.
Because of the high gain of the postamplifier, a very small
offset voltage would shift the decision level in such a way
that the input sensitivity decreases drastically. Therefore a
DC offset compensation circuit is implemented in the
TZA3044, which keeps the input of buffer A3 at its toggle
point in the absence of any input signal.
An input signal level detection is implemented to check if
the input signal is above the user-programmed level.
The outcome of this test is available at the PECL
outputs ST and STQ (TTL for the TZA3044B). This flag
can also be used to prevent the PECL outputs DOUT and
DOUTQ from reacting to noise in the absence of a valid
input signal, by connecting pin STQ to pin JAM. This
guarantees that data will only be transmitted when the
input signal-to-noise ratio is sufficient for low bit error rate
system operation.
PECL logic
The logic level symbol definitions for PECL are shown in
Fig.4.
Input biasing
The inputs, pins DIN and DINQ, are DC biased at
approximately 2.1 V by an internal reference generator
(see Fig.5). The TZA3044 can be DC coupled, but AC
coupling is preferred. In case of DC coupling, the driving
source must operate within the allowable input signal
range (1.3 V to V
CCA
). Also a DC offset voltage of more
than a few millivolts should be avoided, since the internal
DC offset compensation circuit has a limited correction
range.
TZA3044; TZA3044B
If AC coupling is used to remove any DC compatibility
requirement, the coupling capacitors must be large
enough to pass the lowest input frequency of interest.
For example, 1 nF coupling capacitors react with the
internal 4.5 kΩ input bias resistors to yield a lower
−3
dB
frequency of 35 kHz. This then sets a limit on the
maximum number of consecutive pulses that can be
sensed accurately at the system data rate. Capacitor
tolerance and resistor variation must be included for an
accurate calculation.
DC-offset compensation
A control loop connected between the inputs of buffer A3
and amplifier A1 (see Fig.1) will keep the input of buffer A3
at its toggle point in the absence of any input signal.
Because of the active offset compensation which is
integrated in the TZA3044, no external capacitor is
required. The loop time constant determines the lower
cut-off frequency of the amplifier chain, which is set at
approximately 850 Hz.
Input signal level detection
The TZA3044 allows for user-programmable input signal
level detection and can automatically disable the switching
of the PECL outputs if the input signal is below a set
threshold. This prevents the outputs from reacting to noise
in the absence of a valid input signal, and insures that data
will only be transmitted when the signal-to-noise ratio of
the input signal is sufficient for low bit-error-rate system
operation. Complementary PECL (TTL for the TZA3044B)
flags (pins ST and STQ) indicate whether the input signal
is above or below the programmed threshold level.
The input signal is amplified and rectified before being
compared to a programmable threshold reference. A filter
is included to prevent noise spikes from triggering the level
detector. This filter has a nominal 1
µs
time constant and
additional filtering can be achieved by using an external
capacitor between V
CCA
and pin CF (the internal driving
impedance nominally is 25 kΩ). The resultant signal is
then compared to a threshold current through pin RSET.
This current can be set by connecting an external resistor
between V
CCA
and pin RSET, or by forcing a current into
pin RSET (see Fig.6).
1999 Nov 03
5
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