AT25256-10PA-2.7C datasheet, PDF

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AT25256-10PA-2.7C: DescriptionEEPROM, 32KX8, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001BA, DIP-8; Categorystorage storage; File Size176KB，18 Pages; ManufacturerAtmel (Microchip)

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AT25256-10PA-2.7C Overview

EEPROM, 32KX8, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001BA, DIP-8

AT25256-10PA-2.7C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	DIP
package instruction	0.300 INCH, PLASTIC, MS-001BA, DIP-8
Contacts	8
Reach Compliance Code	unknown
ECCN code	EAR99
Maximum clock frequency (fCLK)	2.1 MHz
Data retention time - minimum	200
Durability	100000 Write/Erase Cycles
JESD-30 code	R-PDIP-T8
JESD-609 code	e0
length	9.271 mm
memory density	262144 bit
Memory IC Type	EEPROM
memory width	8
Humidity sensitivity level	1
Number of functions	1
Number of terminals	8
word count	32768 words
character code	32000
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
organize	32KX8
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP8,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3/5 V
Certification status	Not Qualified
Maximum seat height	5.334 mm
Serial bus type	SPI
Maximum standby current	0.000002 A
Maximum slew rate	0.005 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Maximum write cycle time (tWC)	10 ms
write protect	HARDWARE/SOFTWARE
Base Number Matches	1

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Features

•

Serial Peripheral Interface (SPI) Compatible

•

Supports SPI Modes 0 (0,0) and 3 (1,1)

•

Medium-voltage and Standard-voltage Operation

•

– 5.0 (V

= 4.5V to 5.5V)

– 2.7 (V

= 2.7V to 5.5V)

3 MHz Clock Rate

64-byte Page Mode and Byte Write Operation

Block Write Protection

– Protect 1/4, 1/2, or Entire Array

Write Protect (WP) Pin and Write Disable Instructions for

both Hardware and Software Data Protection

Self-timed Write Cycle (5 ms Typical)

High-reliability

– Endurance: 100,000 Write Cycles

– Data Retention: >200 Years

8-lead PDIP, 8-lead JEDEC SOIC and 8-lead EIAJ SOIC Packages

SPI Serial

Automotive

EEPROMs

128K (16,384 x 8)

256K (32,768 x 8)

Description

The AT25128/256 provides 131,072/262,144 bits of serial electrically-erasable pro-

grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits

each. The device is optimized for use in many industrial and commercial applications

where low-power and low-voltage operation are essential. The devices are available in

space saving 8-lead PDIP (AT25128/256), 8-lead JEDEC SOIC (AT25128) and 8-lead

EIAJ SOIC (AT25256) packages. In addition, the entire family is available in 5.0V

(4.5V to 5.5V) and 2.7V (2.7V to 5.5V) versions.

AT25128

AT25256

Pin Configurations

Pin Name

SCK

GND

VCC

HOLD

Function

Chip Select

Serial Data Clock

Serial Data Input

Serial Data Output

Ground

Power Supply

Write Protect

Suspends Serial Input

No Connect

Don't Connect

GND

VCC

HOLD

SCK

8-lead PDIP

GND

VCC

HOLD

SCK

8-lead SOIC

Rev. 3262C–SEEPR–6/03

AT25128/256

Serial Interface

Description

MASTER:

The device that generates the serial clock.

SLAVE:

Because the Serial Clock pin (SCK) is always an input, the AT25128/256

always operates as a slave.

TRANSMITTER/RECEIVER:

The AT25128/256 has separate pins designated for data

transmission (SO) and reception (SI).

MSB:

The Most Significant Bit (MSB) is the first bit transmitted and received.

SERIAL OP-CODE:

After the device is selected with CS going low, the first byte will

be received. This byte contains the op-code that defines the operations to be performed.

INVALID OP-CODE:

If an invalid op-code is received, no data will be shifted into the

AT25128/256, and the serial output pin (SO) will remain in a high impedance state until

the falling edge of CS is detected again. This will reinitialize the serial communication.

CHIP SELECT:

The AT25128/256 is selected when the CS pin is low. When the device

is not selected, data will not be accepted via the SI pin, and the serial output pin (SO)

will remain in a high impedance state.

HOLD:

The HOLD pin is used in conjunction with the CS pin to select the AT25128/256.

When the device is selected and a serial sequence is underway, HOLD can be used to

pause the serial communication with the master device without resetting the serial

sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To

resume serial communication, the HOLD pin is brought high while the SCK pin is low

(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin

is in the high impedance state.

WRITE PROTECT:

The write protect pin (WP) will allow normal read/write operations

when held high. When the WP pin is brought low and WPEN bit is “1”, all write opera-

tions to the status register are inhibited. WP going low while CS is still low will interrupt a

write to the status register. If the internal write cycle has already been initiated, WP

going low will have no effect on any write operation to the status register. The WP pin

function is blocked when the WPEN bit in the status register is “0”. This will allow the

user to install the AT25128/256 in a system with the WP pin tied to ground and still be

able to write to the status register. All WP pin functions are enabled when the WPEN bit

is set to “1”.

3262C–SEEPR–6/03

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