M54HC595
RAD-HARD 8 BIT SHIFT REGISTER
WITH OUTPUT LATCHES (3 STATE)
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 59MHz (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 6mA (MIN.) FOR QA to QH
|I
OH
| = I
OL
= 4mA (MIN.) FOR QH’
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 595
SPACE GRADE-1: ESA SCC QUALIFIED
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
DEVICE FULLY COMPLIANT WITH
SCC-9306-051
DILC-16
FPC-16
ORDER CODES
PACKAGE
DILC
FPC
FM
M54HC595D
M54HC595K
EM
M54HC595D1
M54HC595K1
DESCRIPTION
The M54HC595 is an high speed CMOS 8-BIT
SHIFT
REGISTERS/OUTPUT
LATCHES
(3-STATE) fabricated with silicon gate C
2
MOS
technology.
PIN CONNECTION
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. The storage register has 8 3-STATE
outputs. Separate clocks are provided for both the
shift register and the storage register.
The shift register has a direct-overriding clear,
serial input, and serial output (standard) pins for
cascading. Both the shift register and storage
register use positive-edge triggered clocks. If both
clocks are connected together, the shift register
state will always be one clock pulse ahead of the
storage register.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
June 2004
Rev. 1
1/15
M54HC595
Figure 1: IEC Logic Symbols
Figure 2: Input And Output Equivalent Circuit
Table 1: Pin Description
PIN N°
1, 2, 3, 4, 5,
6, 7, 15
9
10
11
13
14
12
8
16
SYMBOL
QA to QH
QH’
SCLR
SCK
G
SI
RCK
GND
V
CC
NAME AND FUNCTION
Data Outputs
Serial Data Outputs
Shift Register Clear Input
Shift Register Clock Input
Output Enable Input
Serial Data Input
Storage Register Clock
Input
Ground (0V)
Positive Supply Voltage
Table 2: Truth Table
INPUTS
OUTPUTS
SI
X
X
X
L
SCK
X
X
X
SCLR
X
X
L
H
RCK
X
X
X
X
G
H
L
X
X
QA THRU QH OUTPUTS DISABLE
QA THRU QH OUTPUTS ENABLE
SHIFT REGISTER IS CLEARED
FIRST STAGE OF S.R. BECOMES "L" OTHER
STAGES STORE THE DATA OF PREVIOUS
STAGE, RESPECTIVELY
FIRST STAGE OF S.R. BECOMES "H" OTHER
STAGES STORE THE DATA OF PREVIOUS
STAGE, RESPECTIVELY
STATE OF S.R. IS NOT CHANGED
S.R. DATA IS STORED INTO STORAGE
REGISTER
STORAGE REGISTER STATE IS NOT CHANGED
H
X
X
X
X: Don’t Care
H
H
X
X
X
X
X
X
X
X
X
X
2/15
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