M54HC597
RAD-HARD 8 BIT LATCH/SHIFT REGISTER
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 50 MHz (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
=4µA(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 4mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 597
SPACE GRADE-1: ESA SCC QUALIFIED
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
DEVICE FULLY COMPLIANT WITH
SCC-9306-054
DILC-16
FPC-16
ORDER CODES
PACKAGE
DILC
FPC
FM
M54HC597D
M54HC597K
EM
M54HC597D1
M54HC597K1
DESCRIPTION
The M54HC597 is an high speed CMOS 8 BIT
PIPO SHIFT REGISTER fabricated with silicon
gate C
2
MOS technology.
This devices comes in a 16-pin package and
consist of an 8-bit storage latch feeding a parallel
in, serial out 8-bit shift register. Both the storage
register and shift register have positive edge
triggered clocks. The shift register also has direct
load (from storage) and clear inputs.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PIN CONNECTION
June 2004
Rev. 1
1/14
M54HC597
Figure 1: IEC Logic Symbols
Figure 2: Input And Output Equivalent Circuit
Table 1: Pin Description
PIN N°
9
10
11
12
13
10
15, 1, 2, 3, 4,
5, 6, 7
8
16
SYMBOL
QH’
SCLR
SCK
RCK
SLOAD
SI
A to H
GND
V
CC
NAME AND FUNCTION
Serial Data Outputs
Asynchronous Reset
Input (Active LOW)
Shift Clock Input (LOW to
HIGH Edge-triggered)
Storage Clock Input (LOW
to HIGH Edge-triggered)
Parallel Data Input (Active
Low)
Serial Data Input
Parallel Data Inputs
Ground (0V)
Positive Supply Voltage
Table 2: Truth Table
INPUTS
OUTPUT
SI
X
X
L
H
X
X
X
X : Don’t Care
SCK
X
X
SCLR
L
H
H
H
H
SLOAD
H
L
H
H
H
X
X
RCK
X
X
X
X
X
S.R. IS CLEARED TO "L"
INPUT REGISTER DATA IS STORED INTO S.R.
FIRST STAGE OF S.R. BECOMES "L" OTHER STAGES
STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY
FIRST STAGE OF S.R. BECOMES "H" OTHER STAGES
STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY
STATE OF S.R. IS NOT CHANGED
INPUT DATA ON A ~ H LINE IS STORED INTO INPUT REG-
ISTER
STORAGE REGISTER STATE IS NOT CHANGED
X
X
X
X
2/14
M54HC597
Figure 4: Timing Chart
Table 3: Absolute Maximum Ratings
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
25
±
50
300
-65 to +150
265
Unit
V
V
V
mA
mA
mA
mA
mW
°C
°C
I
CC
or I
GND
DC V
CC
or Ground Current
P
D
Power Dissipation
T
stg
T
L
Storage Temperature
Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
4/14
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