M54HC590
RAD-HARD 8 BINARY COUNTER REGISTER
WITH 3 STATE OUTPUT
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED:
f
MAX
= 61 MHz (TYP.) at V
CC
= 6V
LOW POWER DISSIPATION:
I
CC
= 4µA(MAX.) at T
A
=25°C
HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 6mA (MIN) for QA ~ QH OUTPUT
|I
OH
| = I
OL
= 4mA (MIN) for RCO OUTPUT
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
WIDE OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 6V
PIN AND FUNCTION COMPATIBLE WITH
54 SERIES 590
SPACE GRADE-1: ESA SCC QUALIFIED
50 krad QUALIFIED, 100 krad AVAILABLE ON
REQUEST
NO SEL UNDER HIGH LET HEAVY IONS
IRRADIATION
DEVICE FULLY COMPLIANT WITH
SCC-9204-071
DILC-16
FPC-16
ORDER CODES
PACKAGE
DILC
FPC
FM
M54HC590D
M54HC590K
EM
M54HC590D1
M54HC590K1
DESCRIPTION
The M54HC590 is an high speed CMOS 8-BIT
BINARY COUNTER REGISTER (3 STATE)
fabricated with silicon gate C
2
MOS technology.
This device contains an 8-bit binary counter that
feeds an 8-bit storage register. The storage
register has parallel outputs. Separate clocks are
provided for both the binary counter and storage
register. The binary counter features a direct clear
input CCLR and a count enable input CCKEN. For
cascading, a ripple carry output RCO is provided.
Expansion is easily accomplished by tying RCO of
the first stage to CCKEN of the second stage, etc.
Both the counter and register clocks are positive
edge triggered. If the user wishes to connect both
clocks together, the counter state will always be
one count ahead of the register. Internal circuitry
prevents clocking from the clock enable. All inputs
are equipped with protection circuits against static
discharge and transient excess voltage.
PIN CONNECTION
June 2004
Rev. 1
1/16
M54HC590
Figure 1: IEC Logic Symbols
Figure 2: Input And Output Equivalent Circuit
Table 1: Pin Description
PIN N°
1, 2, 3, 4, 5,
6, 7, 15
11
12
13
9
14
10
8
16
SYMBOL
QA to QH
CCK
CCKEN
RCK
RCO
G
CCLR
GND
V
CC
NAME AND FUNCTION
Outputs
Counter Clock Input
Counter Clock Enable
Input
Register Clock Input
Ripple Carry Output
Output Enable Input
Counter Clear Input
Ground (0V)
Positive Supply Voltage
Table 2: Truth Table
INPUTS
OUTPUT
G
H
L
X
X
X
X
X
X
X
X
X
X
RCK
X
X
CCLR
X
X
X
X
L
H
H
H
CCKEN
X
X
X
X
X
L
L
H
X
CCK
X
X
X
X
X
Q OUTPUTS DISABLE
Q OUTPUTS ENABLE
COUNTER DATA IS STORED INTO REGISTER
REGISTER STAGE IS NOT CHANGED
COUNTER CLEAR
ADVANCE ONE COUNT
NO COUNT
NO COUNT
X: Don’t Care
RCO = QA’·QB’·QC’·QD’·QE’·QF’·QG’·QH’ (QA’ to QH’: INTERNAL OUTPUTS OF THE COUNTER)
2/16
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