A29DL16x Series
16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS 3.0 Volt-only,
Preliminary
Document Title
2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No.
0.0
Simultaneous Operation Flash Memory
History
Initial issue
Issue Date
September 28, 2004
Remark
Preliminary
PRELIMINARY (September, 2004, Version 0.0)
AMIC Technology, Corp.
A29DL16x Series
16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS 3.0 Volt-only,
Preliminary
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operations
- Data can be continuously read from one bank while
executing erase/program functions in other bank
- Zero latency between read and write operations
Multiple bank architectures
- Three devices available with different bank sizes (refer to
Table 2)
Package options
-
48-ball TFBGA
-
48-pin TSOP
Top or bottom boot block
Manufactured on 0.18 µm process technology
- Compatible with A29DL16xC/ A29DL16xD devices
Compatible with JEDEC standards
-
Pinout and software compatible with single-power-supply
flash standard
PERFORMANCE CHARACTERISTICS
High performance
-
Access time as fast as 70ns
-
Program time: 7µs/word typical utilizing Accelerate
function
Ultra low power consumption (typical values)
-
2mA active read current at 1MHz
-
10mA active read current at 5MHz
-
200nA in standby or automatic sleep mode
Minimum 1 million write cycles guaranteed per sector
20 Year data retention at 125°C
-
Reliable operation for the life of the system
SOFTWARE FEATURES
Supports Common Flash Memory Interface (CFI)
Erase Suspend/Erase Resume
-
Suspends erase operations to allow programming in
same bank
Software temporary sector/sector block unprotect command
Software sector protect/unprotect command
Simultaneous Operation Flash Memory
Data
Polling and Toggle Bits
-
Provides a software method of detecting the status of
program or erase cycles
Unlock Bypass Program command
-
Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
Any combination of sectors can be erased
Ready/
Busy
output (RY/
BY
)
- Hardware method for detecting program or erase cycle
completion
Hardware reset pin (
RESET
)
- Hardware method of resetting the internal state machine
to reading array data
WP
/ACC input pin
- Write protect (
WP
) function allows protection of two
outermost boot sectors, regardless of sector protect
status
- Acceleration (ACC) function accelerates program timing
Sector protection
- Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program
or erase operation within that sector
- Temporary Sector Unprotect allows changing data in
protected sectors in-system
PRELIMINARY (September, 2004, Version 0.0)
1
AMIC Technology, Corp.
A29DL16x Series
GENERAL DESCRIPTION
The A29DL16x family consists of 16 megabit, 3.0 volt-only
flash memory devices, organized as 1,048,576 words of 16
bits each or 2,097,152 bytes of 8 bits each. Word mode data
appears on I/O
0
–I/O
15
; byte mode data appears on I/O
0
–I/O
7
.
The device is designed to be programmed in-system with the
standard 3.0 volt VCC supply, and can also be programmed
in standard EPROM programmers.
The device is available with an access time of 70, 90, or 120
ns. The devices are offered in 48-pin TSOP and 48-ball Fine-
pitch BGA. Standard control pins—chip enable (
CE
), write
enable (
WE
), and output enable (
OE
)—control normal read
and write operations, and avoid bus contention issues.
The device requires only a
single 3.0 volt power supply
for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
A29DL16x Features
The device offers complete compatibility with the
JEDEC
single-power-supply Flash command set standard.
Commands are written to the command register using
standard microprocessor write timings. Reading data out of
the device is similar to reading from other Flash or EPROM
devices.
The host system can detect whether a program or erase
operation is complete by using the device
status bits:
RY/
BY
pin, I/O
7
(
Data
Polling) and I/O
6
/I/O
2
(toggle bits).
After a program or erase cycle has been completed, the
device automatically returns to reading array data.
The
sector erase architecture
allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection
measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The
hardware sector protection
feature
disables both program and erase operations in any
combination of the sectors of memory. This can be achieved
in-s y s t e m or via programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the
automatic sleep mode.
The system
can also place the device into the
standby mode.
Power
consumption is greatly reduced in both modes.
Simultaneous Read/Write Operations with Zero
Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory space into
two banks. The device can improve overall system
performance by allowing a host system to program or erase
in one bank, then immediately and simultaneously read from
the other bank, with zero latency. This releases the system
from waiting for the completion of program or erase
operations.
The A29DL16x devices uses multiple bank architectures to
provide flexibility for different applications. Three devices are
available with these bank sizes:
Device
DL162
DL163
DL164
Bank 1
2 Mb
4 Mb
8 Mb
Bank 2
14 Mb
12 Mb
8 Mb
PRELIMINARY
(September, 2004, Version 0.0)
2
AMIC Technology, Corp.
A29DL16x Series
Pin Configurations
TSOP (I)
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
RESET
NC
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
I/O
15
(A-1)
I/O
7
I/O
14
I/O
6
I/O
13
I/O
5
I/O
12
I/O
4
VCC
I/O
11
I/O
3
I/O
10
I/O
2
I/O
9
I/O
1
I/O
8
I/O
0
OE
VSS
CE
A0
A29DL16xV
TFBGA
TFBGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
A13
A5
A12
B5
A14
C5
A15
D5
A16
E5
BYTE
F5
I/O
15
(A-1)
G5
VSS
H5
A9
A4
A8
B4
A10
C4
A11
D4
I/O
7
E4
I/O
14
F4
I/O
13
G4
I/O
6
H4
WE
A3
RESET
B3
NC
C3
A19
D3
I/O
5
E3
I/O
12
F3
VCC
G3
I/O
4
H3
RY/BY
A2
WP/ACC
B2
A18
C2
NC
D2
I/O
2
E2
I/O
10
F2
I/O
11
G2
I/O
3
H2
A7
A1
A17
B1
A6
C1
A5
D1
I/O
0
E1
I/O
8
F1
I/O
9
G1
I/O
1
H1
A3
A4
A2
A1
A0
CE
OE
VSS
PRELIMINARY
(September, 2004, Version 0.0)
3
AMIC Technology, Corp.
A29DL16x Series
Block Diagram
VCC
VSS
OE BYTE
Y-Decoder
A0-A19
Upper Bank Address
Upper Bank
Latches and Control Logic
RY/BY
X-Decoder
A0-A19
RESET
WE
CE
BYTE
WP/ACC
STATE
CONTROL
&
COMMAND
REGISTER
Status
I/O
0
-I/O
15
A0-A19
I/O
0
-I/O
15
Control
I/O
0
-I/O
15
X-Decoder
Latches and
Control Logic
Y-Decoder
I/O
0
-I/O
15
A0-A19
Upper Bank
A0-A19
Lower Bank Address
OE BYTE
Pin Descriptions
Pin No.
A0 - A19
I/O
0
- I/O
14
I/O
15
I/O
15
(A-1)
A-1
Description
Address Inputs
Data Inputs/Outputs
Data Input/Output, Word Mode
Logic Symbol
20
A0-A19
16 or 8
I/O
0
-I/O
15
(A-1)
LSB Address Input, Byte Mode
Chip Enable
Write Enable
Output Enable
Hardware Write Protect/Acceleration Pin
Hardware Reset Pin, Active Low
Selects 8-bit or 16-bit Mode
Ready/
BUSY
Output
Ground
3.0 volt-only single power supply
Pin Not Connected Internally
CE
OE
WE
WP/ACC
RESET
BYTE
CE
WE
OE
WP
/ACC
RESET
RY/BY
BYTE
RY/
BY
VSS
VCC
NC
PRELIMINARY
(September, 2004, Version 0.0)
4
AMIC Technology, Corp.
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