The AS7C4098 and AS7C34098 are high performance CMOS 4,194,304-bit Static Random Access Memories (SRAM) organized as
262,144 words × 16 bits. They are designed for memory applications where fast data access, low power, and simple interfacing are
desired.
SRAM
Equal address access and cycle times (t
AA
, t
RC
, t
WC
) of 10/12/15/20/25 ns with output enable access times (t
OE
) of 4/5/5/6/7 ns are ideal
for high performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems.
When CE is High the device enters standby mode. The standard AS7C4098 is guaranteed not to exceed 55 mW power consumption in
CMOS standby mode. Both devices offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0-I/O15 is written on the
rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs
have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) High. The chip drives I/O
pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active,
output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written
and read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are TTL- and CMOS-compatible, and operation is from either a single 5V (AS7C4098) or 3.3V (AS7C34098)
supply. Both devices are available in the JEDEC standard 400-mil, 44-pin SOJ and TSOP II packages.
Absolute maximum ratings
Parameter
Voltage on any input pin relative to GND (7C4098)
Voltage on any input pin relative to GND (7C34098)
Voltage on any I/O pin
Power dissipation
Storage temperature
DC output current
Symbol
V
t
V
t
V
t
P
D
T
stg
I
out
Min
–0.5
–0.5
–0.5
–
–55
–
Max
+7.0
+5.5
V
CC
+ 0.5
1.5
+150
+/−20
Unit
V
V
V
W
o
C
mA
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
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Test/Measurement
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