ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
1
2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC16821
PI74AVCH16821
20-Bit Bus Interface Flip-Flop
with 3-State Outputs
Product Features
•
Designed for low voltage operation, V
CC
= 1.65V to 3.6V
•
Sub 2.0ns delays at 2.5V and 3.3V
•
Dynamic Impedance Control on outputs, current
drive > ±24mA at 2.5V
CC
•
Patented noise reduction circuit
•
I/O Tolerant to 3.6V, Inputs and Outputs for
mixed voltage systems
•
Supports live insertion
•
Industrial operation at -40°C to +85°C
•
Available Packages:
48-pin 240 mil wide plastic TSSOP (A48)
48-pin 173 mil wide plastic TVSOP (K48)
Description
Pericom Semiconductors PI74AVC series of logic circuits are
produced using the Companys advanced 0.35 micron CMOS
technology, achieving industry leading speed.
This 20-bit bus interface flip-flop can be used as two 10-bit flip-
flops or one 20-bit flip-flops. The 20 flip-flops are edge-triggered
D-type flip-flops. On the positive transition of the clock (CLK)
input, the device provides true data at the Q outputs.
A buffered output-enable (OE) input can be used to place the ten
outputs in either a normal logic state (HIGH or LOW level) or a high-
impedance state. In the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The high-impedance state
and increased drive provide the capacity to drive bus lines without
the need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data
can be retained or new data can be entered while the outputs are in
the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pullup resistor; the
minimum value of the resistor is determined by the current sinking
capability of the driver.
The PI74AVCH16821 has Bus Hold which retains the data inputs
last state whenever the data input goes to high impedance preventing
floating inputs and eliminating the need for pullup/down resistors.
Logic Block Diagram
1
OE
1
2
OE
28
1CLK 56
One of Ten
Channels
2CLK 29
One of Ten
Channels
1
Q
1
C
1
1
D
1D
1
55
2
C
1
1
D
2D
1
42
15
2Q
1
TO 9 OTHER CHANNELS
TO 9 OTHER CHANNELS
1
PSXXXX
02/01/99
ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC16821/PI74AVCH16821
20-Bit Bus Interface Flip-Flop
with 3-State Outputs
Product Pin Description
Pin Name
OE
CLK
Dx
Qx
GND
V
CC
Description
Output Enable Input (Active LOW)
Clock Input (Active HIGH)
Data Inputs
3-State Outputs
Ground
Power
Truth Table
(1)
Inputs
OE
L
L
L
H
CLK
H or L
X
D
H
L
X
X
Outputs
Q
H
L
Q
0
Z
Product Pin Configuration
1
QE
1
Q
1
1
Q
2
1
2
3
4
5
6
7
8
9
10
56
55
54
53
52
51
50
49
48
47
1
CLK
1
D
1
1
D
2
Note:
1. H
L
X
Z
↑
n
=
=
=
=
=
=
High Signal Level
Low Signal Level
Irrelevant
High Impedance
LOW-to-HIGH Transition
1,2
GND
1
Q
3
1
Q
4
GND
1
D
3
1
D
4
VCC
1
Q
5
1
Q
6
1
Q
7
VCC
1
D
5
1
D
6
1
D
7
GND
1
Q
8
1
Q
9
1
Q
10
2
Q
1
2
Q
2
2
Q
3
11
56 Pin
46
12
A, V
45
44
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
43
56-PIN
V56
42
A56
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
1
D
8
1
D
9
1
D
10
2
D
1
2
D
2
2
D
3
GND
2
Q
4
2
Q
5
2
Q
6
GND
2
D
4
2
D
5
2
D
6
VCC
2
Q
7
2
Q
8
VCC
2
D
7
2
D
8
GND
2
Q
9
2
Q
10
2
OE
GND
2
D
9
2
D
10
2
CLK
2
PSXXXX
02/01/99
ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC16821/PI74AVCH16821
20-Bit Bus Interface Flip-Flop
with 3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ........................................................... 65°C to +150°C
Ambient Temperature with Power Applied ........................ 40°C to +85°C
Input Voltage Range, V
IN ......................................................
0.5V to V
CC
+0.5V
Output Voltage Range, V
OUT ...............................................
0.5V to V
CC
+0.5V
DC Input Voltage .................................................................... 0.5V to +5.0V
DC Output Current ............................................................................ 100 mA
Power Dissipation .................................................................................. 1.0W
Note:
Stresses greater than those listed under MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
DC Electrical Characteristics
(Over the Operating Range, T
A
= 40°C to +85°C, V
CC
= 3.3V ±10%)
Parame te rs
V
CC
V
IH(3)
V
IL(3)
V
IN(3)
V
OUT(3)
D e s cription
Supply Voltage
Input HIGH Voltage
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
0
0
I
OH
= - 100
m
A, V
CC
= Min. to Max.
O utput
HIGH
Voltage
V
IH
= 1.7V, I
OH
= - 6mA, V
CC
= 2.3V
V
IH
= 1.7V, I
OH
= - 12mA, V
CC
= 2.3V
V
IH
= 2.0V, I
OH
= - 12mA, V
CC
= 2.7V
V
IH
= 2.0V, I
OH
= - 12mA, V
CC
= 3.0V
V
IH
= 2.0V, I
OH
= - 24mA, V
CC
= 3.0V
I
OL
= 100
m
A, V
IL
= Min. to Max.
V
OL
O utput
LO W
Voltage
V
IL
= 0.7V, I
OL
= 6mA, V
CC
= 2.3V
V
IL
= 0.7V, I
OL
= 12mA, V
CC
= 2.3V
V
IL
= 0.8V, I
OL
= 12mA, V
CC
= 2.7V
V
IL
= 0.8V, I
OL
= 24mA, V
CC
= 3.0V
O utput
HIGH
Current
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
3
Te s t Conditions
(1)
M in.
2.3
1.7
2.0
Typ.
(2)
M ax.
3.6
Units
Input LO W Voltage
Input Voltage
O utput Voltage
0.7
0.8
V
CC
V
CC
V
CC
- 0.2
2.0
1.7
2.2
2.4
2.0
0.2
0.4
0.7
0.4
0.55
- 12
- 12
- 24
12
12
24
PSXXXX
02/01/99
V
V
OH
I
OH(3)
mA
I
OL(3)
O utput
LO W
Current
ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC16821/PI74AVCH16821
20-Bit Bus Interface Flip-Flop
with 3-State Outputs
Typ.
(2)
DC Electrical Characteristics-
Continued
(Over the Operating Range, T
A
= 40°C to +85°C, V
CC
= 3.3V ±10%)
Parame te rs De s cription
I
IN
Input Current
Te s t Conditions
(1)
V
IN
= V
CC
or GND, V
CC
= 3.6V
V
IN
= 0.7V, V
CC
= 2.3V
I
IN
(
HOLD
)
Input
Hold
Current
V
IN
= 1.7V, V
CC
= 2.3V
V
IN
= 0.8V, V
CC
= 3.0V
V
IN
= 2.0V, V
CC
= 3.0V
V
IN
= 0 to 3.6V, V
CC
= 3.6V
I
OZ
I
CC
DI
CC
Output Current (3- STATE Outputs)
Supply Current
Supply Current per Input
@ TTL HIGH
Control Inputs
Data Inputs
Outputs
V
OUT
= V
CC
or GND, V
CC
= 3.6V
V
CC
= 3.6V, I
OUT
= 0
m
A,
V
IN
= GND or V
CC
V
CC
= 3.0V to 3.6V
One Input at V
CC
- 0.6V
Other Inputs at V
CC
or GND
V
IN
= V
CC
or GND, V
CC
= 3.3V
V
O
= V
CC
or GND, V
CC
= 3.3V
3.5
6
7
pF
45
- 45
75
- 75
±500
±10
40
750
mA
M in.
M ax.
±5
Units
C
I
C
O
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the
applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient and maximum loading.
3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating.
Timing Requirements over Operating Range
Parame te rs
f
CLOCK
t
W
t
SU
t
H
∆
t/
∆v
(3)
De s cription
Clock Frequency
Pulse Duration CLKHIGH or LOW
Setup Time data before CLK
↑
Hold time data after CLK
↑
Input Transition Rise or Fall
V
CC
= 2.5V ±0.2V
M in.
0
3.3
4.4
0
0
10
M ax.
150
V
CC
= 2.7V
M in.
0
3.3
3.9
0
0
10
M ax.
150
V
CC
= 3.3V ±0.3V
M in.
0
3.3
3.4
0
0
10
ns/v
ns
M ax.
150
Units
MHz
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
4
PSXXXX
02/01/99
ADVANCE INFORMATION
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC16821/PI74AVCH16821
20-Bit Bus Interface Flip-Flop
with 3-State Outputs
Switching Characteristics Over Operating Range
(1)
Parame te rs
f
MAX
t
PD
t
EN
t
DIS
CLK
OE
OE
Q
V
CC
= 2.7V
V
CC
= 2.5V ± 0.2V
From
To
(INPUT) (OUTPUT) M in.
(2)
M ax.
M in.
(
2)
M ax.
150
1.0
1.0
1.4
6.4
7.1
5.9
150
5.3
6.2
5.0
V
CC
= 3.3V ± 0.3V
M in.
(2)
150
1.0
1.0
1.0
4.5
5.1
4.6
ns
M ax.
Units
MHz
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Operating Characteristics, T
A
= 25ºC
Parame te r
C
PD
Power Dissipation
Capacitance
O utputs Enabled
O utputs Disabled
Te s t Conditions
C
L
= 50pF,
f = 10 MHz
V
CC
= 2.5V ±0.2V
36
22
V
CC
= 3.3V ±0.3V
40
24
Typical
Units
pF
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
5
PSXXXX
02/01/99
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