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ASM2P2351AH-24AT

Description
Low Skew Clock Driver, 2351 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 0.209 INCH, SSOP-24
Categorylogic    logic   
File Size479KB,13 Pages
ManufacturerPulseCore Semiconductor Corporation
Download Datasheet Parametric View All

ASM2P2351AH-24AT Overview

Low Skew Clock Driver, 2351 Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, 0.209 INCH, SSOP-24

ASM2P2351AH-24AT Parametric

Parameter NameAttribute value
package instruction0.209 INCH, SSOP-24
Reach Compliance Codeunknown
series2351
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G24
length8.2 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals24
Actual output times10
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE WITH SERIES RESISTOR
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.5 ns
Maximum seat height2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
width5.3 mm
minfmax100 MHz
Base Number Matches1
October 2005
rev 0.2
ASM2P2351AH
1-Line To 10-Line Clock Driver With 3-State Outputs
Features
Low Output Skew, Low Pulse Skew for Clock-
Distribution and Clock-Generation Applications.
Operates at 3.3V Supply Voltage
.
LVTTL-Compatible Inputs and Outputs.
Supports Mixed-Mode Signal Operation.
(5V Input and Output Voltages With 3.3V Supply
Voltage).
Distributes One Clock Input to Ten Outputs.
Outputs have Internal Series Damping Resistor
to Reduce Transmission Line Effects.
Distributed
V
CC
and
Ground
Pins
Reduce
Switching Noise.
Package Options Include Plastic Small-Outline
and Shrink Small-Outline Packages.
Product Description
The ASM2P2351AH is a high-performance clock-driver
circuit that distributes one input (A) to ten outputs (Y)
with minimum skew for clock distribution. The output-
enable (OE) input disables the outputs to a high-
impedance state. Each output has an internal series
damping resistor to improve signal integrity at the load.
The ASM2P2351AH operates at nominal 3.3V Supply
Voltage.
The propagation delays are adjusted at the factory
using the P0 and P1 pins. The factory adjustments
ensure that the part-to-part skew is minimized and is
kept within a specified window. Pins P0 and P1 are not
intended for customer use and should be connected to
GND.
The ASM2P2351AH is characterized for operation
from 0
°
C to 70
°
C.
Logic Diagram (Positive Logic)
5
OE
23
21
19
18
6
A
7 8
PO P1
16
14
11
9
4
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
2
Y10
Alliance Semiconductor
2575 Augustine Drive
Santa Clara, CA
Tel: 408.855.4900
Fax: 408.855.4999
www.alsc.com
Notice: The information in this document is subject to change without notice.

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