a
SUMMARY
Preliminary Technical Data
High performance 32-bit/40-bit floating-point processor
optimized for high performance automotive audio
processing
Audio decoder and post processor-algorithm support with
32-bit floating-point implementations
Nonvolatile memory may be configured to support audio
decoders and post processor-algorithms like PCM, Dolby
®
Digital EX, Dolby Prologic IIx, DTS 96/24, Neo:6, DTS ES
TM
,
MPEG2 AAC, MPEG2 2-channel, MP3, and functions like
bass management, delay, speaker equalization, graphic
equalization, and more. Decoder/post-processor algo-
rithm combination support will vary depending upon the
chip version and the system configurations. Please visit
www.analog.com/SHARC.
SHARC
®
Processor
ADSP-21365/ADSP-21366
Single-Instruction Multiple-Data (SIMD) computational
architecture
On-chip memory—3M bit of on-chip SRAM and a dedicated
4M bit of on-chip mask-programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21365/ADSP-21366 is available with a 333 MHz
core instruction rate and unique audiocentric peripherals
such as the digital audio interface, S/PDIF transceiver,
DTCP (digital transmission content protocol) available on
the ADSP-21365 only, serial ports, 8-channel asynchro-
nous sample rate converter, precision clock generators
and more. For complete ordering information, see
Order-
ing Guide on page 53.
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32-LOCATION
4 BLOCKS OF ON-CHIP MEMORY
BLOCK 0
SRAM
1M BIT
BLOCK 1
SRAM
1M BIT
BLOCK 2
SRAM
0.5M BIT
BLOCK 3
SRAM
0.5M BIT
DAG1
DAG2
PROGRAM
SEQUENCER
ADDR
DATA
ADDR
DATA
ADDR
DATA
ADDR
DATA
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
32
32
64
DM DATA BUS
64
IOA
IOD
IOA
IOD
IOA
IOD
IOA
IOD
PX REGISTER
PROCESSING
ELEMENT
(PEX)
PROCESSING
ELEMENT
(PEY)
IOP REGISTERS
(MEMORY MAPPED)
6
JTAG TEST & EMULATION
SPI
SPORTS
IDP
PCG
TIMERS
SRC
SPDIF
DTCP
SIGNAL
ROUTING
UNIT
I/O PROCESSOR
AND PERIPHERALS
S
Figure 1. Functional Block Diagram—Processor Core
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SEE ADSP-21365/66 MEMORY
AND I/O INTERFACE FEATURES
SECTION FOR DETAILS
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel#: 781.329.4700
www.analog.com
Fax#: 781.326.8703
© 2005 Analog Devices, Inc. All rights reserved.
ADSP-21365/ADSP-21366
KEY FEATURES—PROCESSOR CORE
At 333 MHz (3.0 ns) core instruction rate, the ADSP-
21365/ADSP-21366 performs 2 GFLOPS/666 MMACS
3M bit on-chip SRAM (1M bit in blocks 0 and 1, and 0.50M bit
in blocks 2 and 3) for simultaneous access by the core pro-
cessor and DMA
4M bit on-chip mask-programmable ROM (2M bit in block 0
and 2M bit in block 1)
Dual data address generators (DAGs) with modulo and bit-
reverse addressing
Zero-overhead looping with single-cycle loop setup, provid-
ing efficient program sequencing
Single-Instruction Multiple-Data (SIMD) architecture
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
the assembly level
Parallelism in buses and computational units allows single
cycle execution (with or without SIMD) of a multiply
operation, an ALU operation, a dual memory read or
write, and an instruction fetch
Transfers between memory and core at a sustained 5.4G
bytes/s bandwidth at 333 MHz core instruction rate
Preliminary Technical Data
TDM support for telecommunications interfaces including
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
Up to 12 TDM stream support, each with 128 channels per
frame
Companding selection on a per channel basis in TDM mode
Input data port provides an additional input path to the pro-
cessor core, configurable as eight channels of serial data or
seven channels of serial data and up to a 20-bit wide paral-
lel data channel
Signal routing unit provides configurable and flexible con-
nections between all DAI components–six serial ports, one
SPI port, eight channels of asynchronous sample rate con-
verters, an S/PDIF receiver/transmitter, DTCP (digital
transmission content protocol (ADSP-21365 only), three
timers, an SPI port,10 interrupts, six flag inputs, six flag
outputs, and 20 SRU I/O pins (DAI_Px)
Two serial peripheral interfaces (SPI): primary on dedicated
pins, secondary on DAI pins provide:
master or slave serial boot through primary SPI, full-
duplex operation, master-slave mode multimaster sup-
port, open drain outputs, programmable baud rates, clock
polarities and phases
3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line
INPUT/OUTPUT FEATURES
DMA controller supports:
25 DMA channels for transfers between
ADSP-21365/ADSP-21366 internal memory and a variety
of peripherals
32-bit DMA transfers at peripheral clock speed, in parallel
with full-speed processor execution
Asynchronous parallel port provides access to asynchronous
external memory
16 multiplexed address/data lines support 24-bit address
external address range with 8-bit data or 16-bit address
external address range with 16-bit data
55M byte per sec transfer rate
External memory access in a dedicated DMA channel
8-bit to 32-bit and 16-bit to 32-bit packing options
Programmable data cycle duration: 2 to 31 CCLK
Digital audio interface (DAI) includes six serial ports, two pre-
cision clock generators, an input data port, three timers, an
S/PDIF transceiver, a DTCP cipher (ADSP-21365 only), an 8-
channel asynchronous sample rate converter, an SPI port,
and a signal routing unit
Six dual data line serial ports that operate at up to 50M bits/s
on each data line—each has a clock, frame sync, and two
data lines that can be configured as either a receiver or
transmitter pair
Left-justified sample pair and I
2
S support, programmable
direction for up to 24 simultaneous receive or transmit
channels using two I
2
S-compatible stereo devices per
serial port
DEDICATED AUDIO COMPONENTS
S/PDIF-compatible digital audio receiver/transmitter sup-
ports EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
left-justified, I
2
S or right-justified serial data input with
16-, 18-, 20-, or 24-bit word widths (transmitter)
Two channel mode and single channel double frequency
(SCDF) mode
Digital transmission content protection (DTCP)—a crypto-
graphic protocol for protecting audio content from
unauthorized copying, intercepting, and tampering
(ADSP-21365 only).
Sample rate converter (SRC) Contains a serial input port, de-
emphasis filter, sample rate converter (SRC) and serial out-
put port providing up to
–
128dB SNR performance
Supports left-justified, I
2
S, TDM and right-justified 24-, 20-,
18- and 16-bit serial formats (input)
Pulse-width modulation provides:
16 PWM outputs configured as four groups of four outputs
Supports center-aligned or edge-aligned PWM waveforms
Can generate complementary signals on two outputs in
paired mode or independent signals in nonpaired mode
ROM-based security features include:
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball mini-BGA and 144-lead LQFP packages
(see
Ordering Guide on page 53)
Rev. PrC |
Page 2 of 56 |
May 2005
Preliminary Technical Data
CONTENTS
Summary 1
Key Features—Processor Core ..................................2
Input/Output Features ............................................2
Dedicated Audio Components ..................................2
General Description ..................................................4
ADSP-21365/ADSP-21366 Family Core Architecture .....4
ADSP-21365/ADSP-21366 Memory and I/O Interface Fea-
tures ................................................................6
Development Tools ................................................9
Additional Information ......................................... 11
Pin Function Descriptions ........................................ 12
Address Data Pins as FLAGs .................................. 15
Address/Data Modes ............................................ 15
Boot Modes ........................................................ 15
Core Instruction Rate to CLKIN Ratio Modes ............. 15
ADSP-21365/ADSP-21366 Specifications ..................... 16
Recommended Operating Conditions ....................... 16
Electrical Characteristics ........................................ 16
Maximum Power Dissipation ................................. 17
Absolute Maximum Ratings ................................... 17
ESD Sensitivity .................................................... 17
Timing Specifications ........................................... 18
Output Drive Currents .......................................... 44
Test Conditions ................................................... 44
Capacitive Loading ............................................... 44
Thermal Characteristics ........................................ 45
136-Ball BGA Pin Configurations ............................... 47
144-Lead LQFP Pin Configurations ............................. 50
Package Dimensions ................................................ 51
Ordering Guide ...................................................... 53
ADSP-21365/ADSP-21366
Serial Ports ............................................................30
Input Data Port (IDP) ..............................................33
Parallel Data Acquisition Port (PDAP) .........................34
Sample Rate Converter—Serial Input Port .....................35
Sample Rate Converter—Serial Output Port ..................36
SPDIF Transmitter ..................................................37
SPI Interface—Master ..............................................40
SPI Interface—Slave .................................................41
Thermal Characteristics ............................................45
Ordering Guide ......................................................53
REVISION HISTORY
5/05–Data sheet changed from REV. PrB to REV PrC.
ADSP-21365/ADSP-21366 Internal Memory Space ...........6
Maximum Power Dissipation .................................... 17
Power-Up Sequencing ............................................. 19
Interrupts ............................................................. 21
Core Timer ........................................................... 22
Precision Clock Generator (Direct Pin Routing) ............. 24
Memory Read—Parallel Port ..................................... 26
Memory Write—Parallel Port .................................... 28
Rev. PrC |
Page 3 of 56 |
May 2005
ADSP-21365/ADSP-21366
GENERAL DESCRIPTION
The ADSP-21365/ADSP-21366 SHARC processors are mem-
bers of the SIMD SHARC family of DSPs that feature Analog
Devices’ Super Harvard Architecture. The processors are source
code-compatible with the ADSP-2126x, and ADSP-2116x, DSPs
as well as with first generation ADSP-2106x SHARC processors
in SISD (Single-Instruction, Single-Data) mode. The ADSP-
21365/ADSP-21366 are 32-bit/40-bit floating-point processors
optimized for high performance automotive audio applications
with their large on-chip SRAM and mask-programmable ROM,
multiple internal buses to eliminate I/O bottlenecks, and an
innovative digital audio interface (DAI).
As shown in the functional block diagram
on Page 1,
the
ADSP-21365/ADSP-21366 use two computational units to
deliver a significant performance increase over the previous
SHARC processors on a range of signal processing algorithms.
Fabricated in a state-of-the-art, high speed, CMOS process, the
ADSP-21365/ADSP-21366 processors achieve an instruction
cycle time of 3.0 ns at 333 MHz. With its SIMD computational
hardware, the ADSP-21365/ADSP-21366 can perform two
GFLOPS running at 333 MHz.
Table 1
shows performance benchmarks for the processors run-
ning at 333 MHz.
Table 1. Benchmarks (at 333 MHz)
Speed
(at 333 MHz)
1024 Point Complex FFT (Radix 4, with reversal) 27.9
µs
FIR Filter (per tap)
1
1.5 ns
1
IIR Filter (per biquad)
6.0 ns
Matrix Multiply (pipelined)
[3×3] × [3×1]
13.5 ns
[4×4] × [4×1]
23.9 ns
Divide (y/x)
10.5 ns
Inverse Square Root
16.3 ns
1
Preliminary Technical Data
• Three programmable interval timers with PWM genera-
tion, PWM capture/pulse-width measurement, and
external event counter capabilities
• On-chip SRAM (3M bit)
• On-chip mask-programmable ROM (4M bit)
• 8- or 16-bit parallel port that supports interfaces to off-chip
memory peripherals
• JTAG test access port
The block diagram of the ADSP-21365/ADSP-21366
on Page 7
illustrates the following architectural features:
• DMA controller
• Six full duplex serial ports
• Two SPI-compatible interface ports—primary on dedi-
cated pins, secondary on DAI pins
• Digital audio interface that includes two precision clock
generators (PCG), an input data port (IDP), an S/PDIF
receiver/transmitter, eight channels asynchronous sample
rate converters, DTCP cipher, six serial ports, eight serial
interfaces, a 20-bit parallel input port, 10 interrupts, six flag
outputs, six flag inputs, three timers, and a flexible signal
routing unit (SRU)
Figure 2 on Page 5
shows one sample configuration of a SPORT
using the precision clock generators to interface with an I
2
S
ADC and an I
2
S DAC with a much lower jitter clock than the
serial port would generate itself. Many other SRU configura-
tions are possible.
Benchmark Algorithm
ADSP-21365/ADSP-21366 FAMILY CORE
ARCHITECTURE
The ADSP-21365/ADSP-21366 are code-compatible at the
assembly level with the ADSP-2126x, ADSP-21160 and
ADSP-21161, and with the first generation ADSP-2106x
SHARC processors. The ADSP-21365/ADSP-21366 shares
architectural features with the ADSP-2126x and ADSP-2116x
SIMD SHARC processors, as detailed in the following sections.
Assumes two files in multichannel SIMD mode
The ADSP-21365/ADSP-21366 continues SHARC’s industry-
leading standards of integration for DSPs, combining a high
performance 32-bit DSP core with integrated, on-chip system
features.
The block diagram of the ADSP-21365/ADSP-21366
on Page 1,
illustrates the following architectural features:
• Two processing elements, each of which comprises an
ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycle
SIMD Computational Engine
The ADSP-21365/ADSP-21366 contain two computational pro-
cessing elements that operate as a Single-Instruction Multiple-
Data (SIMD) engine. The processing elements are referred to as
PEX and PEY and each contains an ALU, multiplier, shifter, and
register file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive signal processing algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
Page 4 of 56 |
May 2005
Rev. PrC |
Preliminary Technical Data
ADSP-21366
CLK OU T
C LOC K
2
2
3
C LK IN
X TA L
C LK _C FG1-0
B OOTC FG1 -0
FLA G3-1
RD
WR
FLA G0
A DC
(OPTI ONA L)
C LK
FS
S D AT
A LE
AD 1 5-0
LA TCH
ADSP-21365/ADSP-21366
A DD R
D ATA
OE
WE
CS
PA R A LLEL
POR T
R AM , ROM
BOO T R OM
I /O D EVI CE
CONTROL
DATA
ADDRESS
D A I_P1
DA I_ P2
DA I_ P3
SR U
D A I_P 18
D AI _P 19
DA I_ P2 0
S C LK 0
S FS0
S D 0A
S D 0B
SP OR T0-5
TIME R S
SPD IF
SR C
ID P
S PI
D AC
(OPTI ONA L)
C LK
FS
S D AT
C LK
FS
DAI
R ES ET
PC GA
P CG B
JTA G
6
Figure 2. ADSP-21365/ADSP-21366 System Sample Configuration
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21365/ADSP-21366 features an enhanced Harvard
architecture in which the data memory (DM) bus transfers data
and the program memory (PM) bus transfers both instructions
and data (see
Figure 1 on Page 1).
With the processor’s separate
program and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin-
gle cycle.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended-precision floating-
point, and 32-bit fixed-point data formats.
Instruction Cache
The ADSP-21365/ADSP-21366 include an on-chip instruction
cache that enables three-bus operation for fetching an instruc-
tion and four data values. The cache is selective—only the
instructions whose fetches conflict with PM bus data accesses
are cached. This cache allows full-speed execution of core,
looped operations such as digital filter multiply-accumulates,
and FFT butterfly processing.
Data Register File
A general-purpose data register file is contained in each pro-
cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2136x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.
Data Address Generators With Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21365/ADSP-21366’s two data address generators
(DAGs) are used for indirect addressing and implementing cir-
cular data buffers in hardware. Circular buffers allow efficient
programming of delay lines and other data structures required
Rev. PrC |
Page 5 of 56 |
May 2005
Electronics Design Contest
京公网安备 11010802033920号
EEWORLD
