AS7C25512PFD32A-166BC datasheet, PDF

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AS7C25512PFD32A-166BC: DescriptionStandard SRAM, 512KX32, 3.5ns, CMOS, PBGA165, BGA-165; Categorystorage storage; File Size576KB，24 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]

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AS7C25512PFD32A-166BC Overview

Standard SRAM, 512KX32, 3.5ns, CMOS, PBGA165, BGA-165

AS7C25512PFD32A-166BC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	TBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	3.5 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	166 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	16777216 bit
Memory IC Type	STANDARD SRAM
memory width	32
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX32
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.04 A
Minimum standby current	2.38 V
Maximum slew rate	0.29 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	13 mm
Base Number Matches	1

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March 2004

AS7C25512PFD32A

AS7C25512PFD36A

2.5V 512K

32/36 pipelined burst synchronous SRAM

Features

•

Organization: 524,288 words × 32 or 36 bits

Fast clock speeds to 166 MHz in LVTTL/LVCMOS

Fast clock to data access: 3.5/3.8 ns

Fast OE access time: 3.5/3.8 ns

Fully synchronous register-to-register operation

Dual-cycle deselect

• Single-cycle deselect also available (AS7C251MPFS18A,

AS7C25512PFS32A/AS7C25512PFS36A)

Asynchronous output enable control

Available in 100-pin TQFP package and 165-ball BGA

Individual byte write and global write

Multiple chip enables for easy expansion

•

2.5V core power supply

Linear or interleaved burst control

Snooze mode for reduced power-standby

Common data inputs and data outputs

Boundary scan using IEEE 1149.1 JTAG function

NTD™

pipelined architecture available

(AS7C251MNTD18A, AS7C25512NTD32A/

AS7C25512NTD36A)

•

1 NTD™ is a trademark of Alliance Semiconductor Corporation. All trade-

marks mentioned in this document are the property of their respective

owners.

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

A[18:0]

CLK

CLR

Address

CLK

Burst logic

512K × 32/36

Memory

array

GWE

BWE

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Enable

CLK

Power

down

Enable

delay

CLK

36/32

CE0

CE1

CE2

Output

registers

CLK

Input

registers

CLK

36/32

DQ[a:d]

Selection guide

Minimum cycle time

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

-166

166

3.5

290

-133

7.5

133

3.8

270

Units

MHz

3/25/04, v. 1.0

Alliance Semiconductor

1 of 24

AS7C25512PFD32A

AS7C25512PFD36A

Functional description

The AS7C25512PFD32A/36A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device

organized as 524,288 words x 32/36. It incorporates a two-stage register-register pipeline for highest frequency on any given technology.

Fast cycle times of 6/7.5 ns with clock access times (t

) of 3.5/3.8 ns enable 166 MHz and 133 MHz bus frequencies. Three chip enable

(CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the

processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register

when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data

accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out registers and driven

on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all

subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address

strobes are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved

count sequence. With LBO driven low, the device uses a linear count sequence.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/

36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE

and the appropriate individual byte BWn signals.

BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when

BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented

internally to the next burst address if BWn and ADV are sampled low. This device operates in double-cycle deselect feature during read

cycles.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP

follow.

• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.

• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).

• Master chip enable CE0 blocks ADSP, but not ADSC.

The AS7C25512PFD32A/36A family operates from a core 2.5V power supply. These devices are available in a 100-pin TQFP and 165-ball

BGA.

TQFP and BGA capacitance

Parameter

Input capacitance

I/O capacitance

Symbol

I/O

Test conditions

= 0V

OUT

= 0V

Min

Max

Unit

TQFP and BGA thermal resistance

Description

Thermal resistance

(junction to ambient)

Thermal resistance

(junction to top of case)

1 This parameter is sampled

Conditions

1–layer

Test conditions follow standard test

methods and procedures for measuring

thermal impedance, per EIA/JESD51

4–layer

Symbol

Typical

Units

°C/W

3/25/04, v. 1.0

Alliance Semiconductor

4 of 24

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