Features
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Low Voltage and Standard Voltage Operation: 2.7 (V
CC
= 2.7V to 5.5V)
Internally Organized 128 x 8
Two-wire Serial Interface
Bidirectional Data Transfer Protocol
1 MHz (2.7V, 5V) Compatibility
4-Byte Page Write Mode
Self-Timed Write Cycle (5 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
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Automotive Grade and Lead-Free/Halogen-Free Devices Available
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8-lead PDIP, 8-lead JEDEC SOIC, 8-lead TSSOP Packages
Description
The AT24C11 provides 1024 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 128 words of 8 bits each. The device is
optimized for use in many automotive applications where low power and low voltage
operation are essential. The AT24C11 is available in space saving 8-lead PDIP, 8-lead
JEDEC SOIC, and 8-lead TSSOP packages and is accessed via a Two-wire serial
interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V).
Table 1.
Pin Configuration
Pin Name
NC
SDA
SCL
TEST
Function
No Connect
Serial Data
Serial Clock Input
Test Input (GND or VCC)
8-lead TSSOP
Two-wire
Automotive
Temperature
Serial EEPROM
1K (128 x 8)
AT24C11
NC
NC
NC
GND
1
2
3
4
8
7
6
5
VCC
TEST
SCL
SDA
8-lead SOIC
8-lead PDIP
NC
NC
NC
GND
1
2
3
4
8
7
6
5
VCC
TEST
SCL
SDA
NC
NC
NC
GND
1
2
3
4
8
7
6
5
VCC
TEST
SCL
SDA
Rev. 5093C–SEEPR–09/06
1
Absolute Maximum Ratings*
Operating Temperature..................................–55°C to +125°C
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Figure 1.
Block Diagram
2
AT24C11
5093C–SEEPR–09/06
AT24C11
Pin Description
SERIAL CLOCK (SCL):
The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA):
The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
Memory Organization
AT24C11, 1K SERIAL EEPROM:
Internally organized with 32 pages of 4 bytes each.
The 1K requires a 7-bit data word address for random word addressing.
Table 2.
Pin Capacitance
Applicable over recommended operating range from T
A
= 25°C, f = 1.0 MHz, V
CC
= +2.7V to +5.5V
Symbol
C
I/O
C
IN
Test Condition
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
Max
8
6
Units
pF
pF
Condition
V
I/O
= 0V
V
IN
= 0V
Table 3.
DC Characteristics
Applicable over recommended operating range from: T
AE
=
–
40°C to +125°C, V
CC
= +2.7V to +5.5V (unless otherwise
noted)
Symbol
V
CC1
V
CC2
I
CC
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
I
LI
I
LO
V
IL
V
IH
V
OL2
V
OL1
Note:
Parameter
Supply Voltage
Supply Voltage
Supply Current V
CC
= 5.0V
Supply Current V
CC
= 5.0V
Standby Current V
CC
= 1.8V
Standby Current V
CC
= 2.5V
Standby Current V
CC
= 2.7V
Standby Current V
CC
= 5.0V
Input Leakage Current
Output Leakage Current
Input Low Level
(1)
Input High Level
(1)
Output Low Level V
CC
= 3.0V
Output Low Level V
CC
= 1.8V
I
OL
= 2.1 mA
I
OL
= 0.15 mA
READ at 100 kHz
WRITE at 100 kHz
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
IN
= V
CC
or V
SS
V
OUT
= V
CC
or V
SS
–0.6
V
CC
×
0.7
Test Condition
Min
2.7
4.5
0.4
2.0
0.6
1.4
1.6
8.0
0.10
0.05
Typ
Max
5.5
5.5
1.0
3.0
3.0
4.0
4.0
18.0
3.0
3.0
V
CC
×
0.3
V
CC
+ 0.5
0.4
0.2
Units
V
V
mA
mA
µA
µA
µA
µA
µA
µA
V
V
V
V
1. V
IL
min and V
IH
max are reference only and are not tested.
3
5093C–SEEPR–09/06
Table 4.
AC Characteristics
Applicable over recommended operating range from T
A
=
–
40°C to +125°C, V
CC
= +2.7V
to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted)
2.7V, 5.0V
Symbol
f
SCL
t
LOW
t
HIGH
t
AA
t
BUF
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R
t
F
t
SU.STO
t
DH
t
WR
Endurance
(1)
Note:
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Time the bus must be free before a new
transmission can start
(1)
Start Hold Time
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time
(1)
Inputs Fall Time
(1)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
5.0V, 25°C, Page Mode
1M
0.25
50
5
0.4
0.4
0.05
0.5
0.25
0.6
0
100
0.3
100
0.55
Min
Max
1000
Units
kHz
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
Write
Cycles
1. This parameter is ensured by characterization only.
4
AT24C11
5093C–SEEPR–09/06
AT24C11
Device Operation
CLOCK and DATA TRANSITIONS:
The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (see
Figure 4 on page 6). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION:
A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 7).
STOP CONDITION:
A low-to-high transition of SDA with SCL high is a stop condition
which terminates all communications. After a read sequence, the stop command will
place the EEPROM in a standby power mode (see Figure 5 on page 7).
ACKNOWLEDGE:
All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. Any device on the system bus receiving data (when com-
municating with the EEPROM) must pull the SDA bus low to acknowledge that it has
successfully received each word. This must happen during the ninth clock cycle after
each word received and after all other system devices have freed the SDA bus. The
EEPROM will likewise acknowledge by pulling SDA low after receiving each address or
data word (see Figure 6 on page 7).
STANDBY MODE:
The AT24C11 features a low power standby mode which is enabled:
(a) upon power-up and (b) after the receipt of the STOP bit and the completion of any
internal operations.
MEMORY RESET:
After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
5
5093C–SEEPR–09/06
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