The AS7C33128NTD36A family is a high performance CMOS 4 Mbit synchronous Static Random Access Memory (SRAM) organized as
131,072 words × 32 or 36 bits and incorporates a LATE LATE Write.
This variation of the 4Mb sychronous SRAM uses the No Turnaround Delay (NTD
™
) architecture, featuring an enhanced write operation that
improves bandwidth over pipeline burst devices. In a normal pipeline burst device, the write data, command, and address are all applied to the
device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to
become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write
operations.
NTD
™
devices use the memory bus more efficiently by introducing a write 'latency' which matches the two (one) cycle pipeline
(flowthrough) read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With
NTD
™
, write and read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes.
Write enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock
cycles later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for
normal operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs (refer to
synchronous truth table on page 4.) In pipeline mode, a two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV/LD (burst advance) input to perform burst read, write and deselect operations. When ADV/LD is high, external addresses, chip
select, R/W pins are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device
operations, including burst, can be stalled using the CEN=1, the clock enable input.
The AS7C33128NTD36A and AS7C33128NTD32A operate with a 3.3V ± 5% power supply for the device core (V
DD
). DQ circuits use a
separate power supply (V
DDQ
) that operates across 3.3V or 2.5V ranges. These devices are available in a 100-pin 14×20 mm TQFP package.
Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
Address and control pins
I/O pins
Test conditions
V
in
= 0V
V
in
= V
out
= 0V
5
7
Max
Unit
pF
pF
Burst Order
Interleaved Burst Order
Starting Address
First increment
Second increment
Third increment
00
01
10
11
LBO=1
01
10
00
11
11
00
10
01
11
10
01
00
Starting Address
First increment
Second increment
Third increment
Linear Burst Order
00
01
10
11
LBO=0
01
10
10
11
11
00
00
01
11
00
01
10
Y
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Signal descriptions
Signal
CLK
CEN
A, A0, A1
DQ[a,b,c,d]
CE0, CE1,
CE2
ADV/LD
R/W
BW[a,b,c,d]
OE
LBO
FT
ZZ
NC
I/O Properties Description
I
I
I
I/O
I
I
I
I
I
I
I
I
-
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
STATIC
ASYNC
-
Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.
Clock enable. When de-asserted HIGH, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are
ignored when ADV/LD is HIGH.
Advance or Load. When sampled HIGH, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When LOW, a new
address is loaded.
A HIGH during LOAD initiates a READ operation. A LOW during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is HIGH.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
Asynchronous output enable. I/O pins are not driven when OE is inactive.
Count mode. When driven High, count sequence follows Intel XOR convention. When
driven Low, count sequence follows linear convention. This input should be static when the
device is in operation.
Flow-through mode.When low, enables single register flow-through mode. Connect to V
DD
if unused or for pipelined operation.
Snooze. Places device in low power mode; data is retained. Connect to VSS if unused.
No connects. Note that pin 83 & 84 will be used for future address expansion to 8 Mb
and16Mb density.
Absolute maximum ratings
Parameter
Power supply voltage relative to VSS
Input voltage relative to VSS (input pins)
Input voltage relative to VSS (I/O pins)
Power dissipation
DC output current
Storage temperature (plastic)
Temperature under bias (Junction)
Symbol
V
DD
, V
DDQ
V
IN
V
IN
P
D
I
OUT
T
stg
T
bias
Min
–0.5
–0.5
–0.5
–
–
–65
–65
Max
+4.6
V
DD
+ 0.5
V
DDQ
+ 0.5
1.8
50
+150
+135
Unit
V
V
V
W
mA
o
C
o
C
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.
Y
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Synchronous truth table
CE0
H
X
X
L
L
X
X
CE1
X
L
X
H
H
X
X
CE2
X
X
H
L
L
X
X
ADV/
LD
L
L
L
L
L
H
X
R/W BW[a:d]
X
X
X
H
L
X
X
X
X
X
X
L
X
1
X
OE
X
X
X
X
X
X
X
CEN
L
L
L
L
L
L
H
Address source
NA
NA
NA
External
External
Burst counter
Stall
CLK
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Operation
Deselect, high-Z
Deselect, high-Z
Deselect, high-Z
Begin read
Begin write
Burst
2
Inhibit the CLK
Key: X = Don’t Care, L = Low, H = High.
1. Should be low for Burst write, unless a specific byte/s need/s to be inhibited
2. Refer to state diagram below.
6WDWH 'LDJUDP IRU 17' 65$0
Burst
Read
Read
Read
Burst
Read
Dsel
Burst
Dse
l
Rea
d
Dsel
Dsel
Burst
ad
Re
e
W
rit
Read
Write
Write
Write
Write
ite
Wr
Burst
l
Dse
Burst
Write
Dsel
Burst
TQFP thermal resistance
Description
Thermal resistance
(Junction to Ambient)
1
Thermal resistance
(Junction to Top of Case)
1
7KLV SDUDPHWHU LV VDPSOHG
Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
Symbol
θ
JA
θ
JC
Typical
40
8
Units
°C/W
°C/W
Y
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Recommended operating conditions
Parameter
Supply voltage
3.3V I/O supply
voltage
2.5V I/O supply
voltage
Address and
control pins
I/O pins
Ambient operating temperature
Symbol
V
DD
VSS
V
DDQ
VSSQ
V
DDQ
VSSQ
V
IH
V
IL
V
IH
V
IL
T
A
Min
3.135
0.0
3.135
0.0
2.35
0.0
2.0
–0.5
2
2.0
-0.5
2
0
Nominal
3.3
0.0
3.3
0.0
2.5
0.0
–
–
–
–
–
Max
3.465
0.0
3.465
0.0
2.65
0.0
V
DD
+ 0.3
0.8
V
DDQ
+ 0.3
0.8
70
°C
Unit
V
V
V
V
V
V
V
Input voltages
1
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V operation, contact factory for input specifications.
2 V
IL
min. = –2.0V for pulse width less than 0.2 x t
RC
.
DC electrical characteristics for 3.3V I/O operation
200
Parameter
Input leakage current
1
Output leakage
current
183
2
2
–
–
–
–
–
–
–
2.4
2
2
540
140
30
30
0.4
-
–
–
–
–
–
–
–
166
2
2
475
130
30
30
0.4
–
–
–
–
–
–
–
–
133
2
2
425
100
30
30
0.4
–
–
–
–
–
–
–
–
100
2
2
325
90
30
30
0.4
–
µA
µA
mA
mA
mA
mA
V
V
Sym Test conditions
|
I
LI
|
|
I
LO
|
V
DD
= Max, V
in
= VSS to V
DD
OE
≥
V
IH,
V
DD
= Max,
V
out
= VSS to V
DD
CE = V
IL
, CE = V
IH
, CE = V
IL
,
f
=
f
max,
I
out
= 0 mA
Deselected,
f
=
f
max
Deselected,
f
=
0,
all V
IN
≤
0.2V or
≥
V
DD
- 0.2V
Deselected, f=f
Max
, ZZ
≥
V
DD
-
0.2V All V
IN
≤
V
IL
or
≥
V
IH
I
OL
= 8 mA, V
DDQ
= 3.6V
I
OH
= –4 mA, V
DDQ
= 3.0V
Min Max Min Max Min Max Min Max Min Max Unit
–
–
–
–
–
–
–
2.4
Operating power supply
I
CC
current
I
SB
Standby power supply
current
I
SB1
I
SB2
Output voltage
V
OL
V
OH
570
160
30
30
0.4
-
2.4
2.4
2.4
1 LBO pin has an internal pull-up and input leakage =
±
10 ua.
Note: ICC given with no output loading. ICC increases with faster cycle times and greater output loading.
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