December 2002
Advance Information
®
AS7C25512PFS32A
AS7C25512PFS36A
2.5V 512K
×
32/36 pipelined burst synchronous SRAM
Features
•
•
•
•
•
•
•
•
•
•
•
•
Organization: 524,288 words × 32 or 36 bits
Fast clock speeds to 250MHz in LVTTL/LVCMOS
Fast clock to data access: 2.6/2.8/3/3.4 ns
Fast OE access time: 2.6/2.8/3/3.4 ns
Fully synchronous register-to-register operation
Single register flow-through mode
Single-cycle deselect
Asynchronous output enable control
Available in 100-pin TQFP package and 165-ball BGA
Individual byte write and global write
Multiple chip enables for easy expansion
2.5V core power supply
•
•
•
•
•
Linear or interleaved burst control
Snooze mode for reduced power-standby
Common data inputs and data outputs
Boundary scan using IEEE 1149.1 JTAG function
NTD™
1
pipelined architecture available
(AS7C251MNTD18A, AS7C25512NTD32A/
AS7C25512NTD36A)
1 NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective owners.
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[18:0]
19
CLK
CE
CLR
D
CE
Address
register
CLK
D
Q0
Burst logic
Q1
19
Q
17
19
512K × 32/36
Memory
array
GWE
BWE
BW
d
DQ
d
Q
Byte write
registers
CLK
D
DQ
c
Q
Byte write
registers
CLK
DQ
b
Q
Byte write
registers
CLK
D
DQ
Q
a
Byte write
registers
CLK
D
Enable
CE
register
CLK
Power
down
D
Enable
Q
delay
register
CLK
Q
D
36/32
36/32
BW
c
BW
b
BW
a
CE0
CE1
CE2
4
OE
Output
registers
CLK
Input
registers
CLK
ZZ
OE
FT
36/32
DQ[a:d]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-250
4
250
2.6
450
160
70
-225
4.4
225
2.8
425
150
70
-200
5
200
3.0
400
130
70
-166
6
166
3.4
350
120
70
Units
ns
MHz
ns
mA
mA
mA
12/2/02, v. 0.9.1
Alliance Semiconductor
1 of 21
Copyright © Alliance Semiconductor. All rights reserved.
AS7C25512PFS32A
AS7C25512PFS36A
®
Pin and ball assignment
100-pin TQFP - top view
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Ball assignment for 165-ball BGA for 512K x 36
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
NC
NC
DQPc
DQc
DQc
DQc
DQc
FT
DQd
DQd
DQd
DQd
DQPd
NC
LBO
2
A
A
NC
3
CE0
CE1
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
/%2
$
$
$
$
$
$
1&
1&
9
66
9
''
$
$
$
$
$
$
$
$
$
4
BWc
BWd
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
5
BWb
BWa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
Vss
Vss
Vss
Vss
NC
TDI
TMS
6
CE2
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
A1
1
A0
1
7
BWE
GWE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
TDO
TCK
8
ADSC
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
9
ADV
ADSP
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
A
A
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
NC
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
1 A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
12/2/02, v. 0.9.1
Alliance Semiconductor
2 of 21
AS7C25512PFS32A
AS7C25512PFS36A
®
Functional description
The AS7C25512PFS32A/36A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device organized as
524,288 words x 32/36. It incorporates a two-stage register-register pipeline for highest frequency on any given technology.
Fast cycle times of 4/4.4/5/6 ns with clock access times (t
CD
) of 2.6/2.8/3/3.4 ns enable 250, 225, 200, and 166 MHz bus frequencies.
Three chip enable (CE) inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe
(ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register
when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data accessed
by the current address registered in the address registers by the positive edge of CLK are carried to the data-out registers and driven on the
output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent
clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address strobes are high.
Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved count sequence. With
LBO driven low, the device uses a linear count sequence.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/
36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE
and the appropriate individual byte BWn signals.
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when
BWn is sampled lOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented internally
to the next burst address if BWn and ADV are sampled low. This device operates in single-cycle deselect feature during read cycles.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.
• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).
• Master chip enable CE0 blocks ADSP, but not ADSC.
The AS7C33512PFS32A/36A family operates from a core 2.5V power supply. These devices are available in a 100-pin TQFP and 165-ball BGA.
TQFP and BGA capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
Signals
Address and control pins
I/O pins
Test conditions
V
IN
= 0V
V
OUT
= 0V
Max
5
7
Unit
pF
pF
12/2/02, v. 0.9.1
Alliance Semiconductor
3 of 21
AS7C25512PFS32A
AS7C25512PFS36A
®
Signal descriptions
Pin
CLK
A0–A19
I/O Properties Description
I
I
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
SYNC
SYNC
SYNC
Test Clock
STATIC
ASYNC
Clock. All inputs except OE, FT, ZZ, and LBO are synchronous to this clock.
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.
Data. Driven as output when the chip is enabled and when OE is active.
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is
inactive, ADSP is blocked. Refer to the “Synchronous truth table” for more information.
Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges
when ADSC is active or when CE0 and ADSP are active.
Address strobe processor. Asserted low to load a new address or to enter standby mode.
Address strobe controller. Asserted low to load a new address or to enter standby mode.
Advance. Asserted low to continue burst read/write.
Global write enable. Asserted low to write all 32/36 and 18 bits. When high, BWE and
BW[a:d] control write enable.
Byte write enable. Asserted low with GWE high to enable effect of BW[a:d] inputs.
Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If
any of BW[a:d] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a:d]
are inactive, the cycle is a read cycle.
Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.
Count mode. When driven high, count sequence follows Intel XOR convention. When driven
low, count sequence follows linear convention. This signal is internally pulled high.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK (BGA
only).
Test Clock. All inputs are sampled on the rising edge of TCK. All outputs are driven from the
falling edge of TCK.
Flow-through mode.When low, enables single register flow-through mode. Connect to V
DD
if
unused or for pipelined operation.
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
DQ[a,b,c,d] I/O
CE0
CE1, CE2
ADSP
ADSC
ADV
GWE
BWE
BW[a,b,c,d]
OE
LBO
TDO
TDI
TMS
TCK
FT
ZZ
I
I
I
I
I
I
I
I
I
I
O
I
I
I
I
I
Write enable truth table (per byte)
Function
Write All Bytes
Write Byte a
Write Byte c and d
Read
GWE
L
H
H
H
H
H
BWE
X
L
L
L
H
L
BWa
X
L
L
H
X
H
BWb
X
L
H
H
X
H
BWc
X
L
H
L
X
H
BWd
X
L
H
L
X
H
.H\
X = don’t care, L = low, H = high, n = a, b, c, d;
BWE
,
BWn
= internal write signal.
12/2/02, v. 0.9.1
Alliance Semiconductor
4 of 21
AS7C25512PFS32A
AS7C25512PFS36A
®
Burst sequence table
Interleaved burst address
A1 A0 A1 A0 A1 A0
st
00
01
10
1 Address
2
nd
Address
01
00
11
3
rd
Address
10
11
00
4
th
Address
11
10
01
A1 A0
11
10
01
00
Linear burst address
A1 A0 A1 A0
00
01
01
10
10
11
11
10
A1 A0
10
11
00
01
A1 A0
11
00
01
10
1 Address
2
nd
Address
3
rd
Address
4
th
Address
st
Synchronous truth table
CE0
1
H
L
L
L
L
L
L
L
L
X
X
X
X
H
H
H
H
L
X
H
X
H
CE1
X
L
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
CE2
X
X
X
H
H
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
X
X
ADSP
X
L
H
L
H
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
ADSC
L
X
L
X
L
X
X
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
ADV
X
X
X
X
X
X
X
X
X
L
L
H
H
L
L
H
H
X
L
L
H
H
BWn
2
OE
X
X
X
X
X
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
Address accessed
NA
NA
NA
NA
NA
External
External
External
External
Next
Next
Current
Current
Next
Next
Current
Current
External
Next
Next
Current
Current
CLK
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Operation
Deselect
Deselect
Deselect
Deselect
Deselect
Begin read
Begin read
Begin read
Begin read
Continue read
Continue read
Suspend read
Suspend read
Continue read
Continue read
Suspend read
Suspend read
Begin write
Continue write
Continue write
Suspend write
Suspend write
DQ
Hi
−
Z
Hi
−
Z
Hi
−
Z
Hi
−
Z
Hi
−
Z
Hi
−
Z
3
Hi
−
Z
Hi
−
Z
3
Hi
−
Z
Q
Hi
−
Z
Q
Hi
−
Z
Q
Hi
−
Z
Q
Hi
−
Z
D
4
D
D
D
D
X
X
X
X
X
X
X
F
F
F
F
F
F
F
F
F
F
T
T
T
T
T
1
X = don’t care, L = low, H = high
2
See "Write enable truth table (per byte)," on page 4 for more information.
3
Q in flow-through mode.
4
For write operation following a READ,
OE
must be high before the input data set up time and held high throughout the input hold time
12/2/02, v. 0.9.1
Alliance Semiconductor
5 of 21
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