UTC5-201-5 datasheet, PDF - EEWORLD Datasheet

UTC5-201-5: DescriptionWide Band Low Power Amplifier, 10MHz Min, 500MHz Max,; CategoryWireless rf/communication Radio frequency and microwave; File Size77KB，3 Pages; ManufacturerHP（Keysight）; Websitehttp://www.semiconductor.agilent.com/

Download Datasheet Parametric View All

UTC5-201-5 Overview

Wide Band Low Power Amplifier, 10MHz Min, 500MHz Max,

Parameter Name	Attribute value
Reach Compliance Code	unknown
Characteristic impedance	50 Ω
structure	MODULE
Maximum operating frequency	500 MHz
Minimum operating frequency	10 MHz
Maximum operating temperature	50 °C
Minimum operating temperature
RF/Microwave Device Types	WIDE BAND LOW POWER
Maximum voltage standing wave ratio	2
Base Number Matches	1

[I contribute to the Xilinx Resource Center] A large amount of Verilog source code: A lot of Verilog source codeVerilog HDL 程序举例一，基本组合逻辑功能：双向管脚（clocked bidirectional pin） Verilog HDL: Bidirectional PinThis example implements a clocked bidirectional pin in Verilog HDL. The value of ...; wanghongyang FPGA/CPLD

Slow display speed: Why does the display speed slow down after I turn on the "average sampling" mode or set a longer persistence time when using Dingyang oscilloscope?...; lily608487 Test/Measurement

Scattered: Can ITU656 data without VSYNC/HREF trigger the CAMERA interrupt of S3C6410?: Can ITU656 data without VSYNC/HREF trigger the S3C6410 CAMERA interrupt? How to configure the S3C6410 CAMERA interface? What are the requirements for the CAMERA input? Can it be the standard 720*576 P...; eekingking Embedded System

My Beaglebone learning journey: Organize the previous posts and make a general post to facilitate communication.1. BeagleBone Hardware Performance Test_Weekly Planhttps://bbs.eeworld.com.cn/thread-324885-1-1.html 2. BeagleBone hardw...; chenzhufly DSP and ARM Processors

How to solve the glitch: [font=黑体][size=5]vcc is a fixed level I set, q1 is a sine wave generated by counter + rom, alb is the output waveform after vcc and q1 pass through the comparator, q1 No code? How to solve the glitch...; xmllf FPGA/CPLD

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components