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V62C1802096L-85V

Description
Standard SRAM, 256KX8, 85ns, CMOS, PDSO32, 8 X 13.40 MM, PLASTIC, STSOP-32
Categorystorage    storage   
File Size86KB,9 Pages
ManufacturerMosel Vitelic Corporation ( MVC )
Websitehttp://www.moselvitelic.com
Download Datasheet Parametric View All

V62C1802096L-85V Overview

Standard SRAM, 256KX8, 85ns, CMOS, PDSO32, 8 X 13.40 MM, PLASTIC, STSOP-32

V62C1802096L-85V Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
Parts packaging codeTSOP
package instructionTSOP1, TSSOP32,.56,20
Contacts32
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time85 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G32
JESD-609 codee0
length12.4 mm
memory density2097152 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP1
Encapsulate equivalent codeTSSOP32,.56,20
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply2 V
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum standby current0.00001 A
Minimum standby current1.8 V
Maximum slew rate0.02 mA
Maximum supply voltage (Vsup)2.2 V
Minimum supply voltage (Vsup)1.8 V
Nominal supply voltage (Vsup)2 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width8 mm
Base Number Matches1
V62C1802096L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
• Ultra Low-power consumption
- Active: 25mA at 70ns
- Stand-by: 10
µ
A
(CMOS input/output)
2
µ
A
CMOS input/output, L version
• Single + 1.8V to 2.2V Power Supply
• Equal access and cycle time
• 70/85/100/150 ns access time
• Easy memory expansion with CE1, CE2
and OE inputs
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
• Package available: 32-TSOP1 / STSOP
Functional Description
The V62C1802096L is a low power CMOS Static RAM orga-
nized as 262,144 words by 8 bits. Easy memory expansion is p-
rovided by an active LOW CE1 , an active HIGH CE2, an act-
ive LOW OE , and Tri-state I/O’s. This device has an auto-
matic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip E-
nable 1 (CE1 ) with Write Enable (WE ) LOW, and Chip En-
able 2 (CE2) HIGH. Reading from the device is performed
by taking Chip Enable 1 (CE1 ) with Output Enable
(OE ) LOW while Write Enable (WE ) and Chip Enable 2
(CE2) is HIGH. The I/O pins are placed in a high-imped-
ance state when the device is deselected: the outputs are
disabled during a write cycle.
The V62C1802096LL comes with a 1V data retention feature
and Lower Standby Power. The V62C1802096L is available in
a 32-pin 8 x 13.4 & 8 x 20 mm TSOP1 / STSOP packages.
Logic Block Diagram
32-Pin TSOP1 / STSOP
A
11
A
9
A
8
A
13
WE
CE
2
A
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE1
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
GND
I/O
3
I/O
2
I/O
1
A
0
A
1
A
2
A
3
INPUT BUFFER
A
0
ROW DECODER
SENSE AMP
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A9
I/O8
Vcc
A17
A
16
A
14
A
12
A
7
A
6
Cell Array
I/O1
A
5
A
4
COLUMN DECODER
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
CONTROL
CIRCUIT
OE
WE
CE1
CE2
1
REV. 1.1
April
2001 V62C1802096L(L)
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