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SYS84000RKXLI-12

Description
SRAM Module, 4MX8, 120ns, CMOS, PSMA38, PLASTIC, SIP-38
Categorystorage    storage   
File Size137KB,7 Pages
ManufacturerMOSAIC
Websitehttp://www.mosaicsemi.com/
Download Datasheet Parametric View All

SYS84000RKXLI-12 Overview

SRAM Module, 4MX8, 120ns, CMOS, PSMA38, PLASTIC, SIP-38

SYS84000RKXLI-12 Parametric

Parameter NameAttribute value
Parts packaging codeSIP
package instruction,
Contacts38
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time120 ns
JESD-30 codeR-PSMA-T38
memory density33554432 bit
Memory IC TypeSRAM MODULE
memory width8
Number of functions1
Number of terminals38
word count4194304 words
character code4000000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize4MX8
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formTHROUGH-HOLE
Terminal locationSINGLE
Base Number Matches1
4M x 8 SRAM MODULE
SYS84000RKX - 70/85/10/12
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 1.6 : January 1999
Features
Access Times of 70/85/100/120 ns.
Low Power Disipation:
Operating
665 mW (Max.)
Standby-L Version (CMOS) 4.84mW (Max.)
5 Volt Supply ± 10%.
Completely Static Operation.
Equal Access and Cycle Times.
Low Voltage V
CC
Data Retention.
On-board Decoding & Capacitors.
38 Pin Single-In-Line package (SIP).
Upgrade path to SYS88000RKX (64Mbits).
Description
The SYS84000RKX is a plastic 32Mbit Static RAM
Module housed in a standard 38 pin Single In-Line
package organised as 4M x 8 with access times of 70,
85,100, or 120 ns.
The module is constructed using eight 512Kx8 SRAMs
in TSOPII packages mounted onto both sides of an FR4
epoxy substrate. This offers an extremely high PCB
packing density.
The device is offered in standard and low power versions,
with the -L module having a low voltage data retention
mode for battery backed applications. Buffering is
provided on the module to reduce the output capacitance
to 8pF(Typ).
Note: CS and OE on the module, should be used
with care to avoid on and off board bus contention.
Block Diagram
Pin Definition
NC
A20
Vcc
WE
D2
D3
D0
A1
A2
A3
A4
GND
D5
A10
A11
A5
A13
A14
A19
CS
A15
A16
A12
A18
A6
D1
GND
A0
A7
A8
A9
D7
D4
D6
A17
Vcc
OE
A21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
OE
WE
A0 - A18
512K x 8
SRAM
CS
CS
CS
CS
T/R
A19
A20
A21
Q0~3
DECODER
Q4~7
D0 - D7
D0 - D7
/8
CS
CS
512K x 8
SRAM
OE
CS
CS
CS
Pin Functions
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power (+5V)
Ground
A0 - A21
D0 - D7
CS
WE
OE
NC
V
CC
GND
Package Details
Plastic 38 pin Single-In-Line (SIP)
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