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VP464641641BTGC-10

Description
Synchronous DRAM Module, 4MX64, 7ns, CMOS, SODIMM-144
Categorystorage    storage   
File Size211KB,32 Pages
ManufacturerVanguard International Semiconductor Corporation
Websitehttp://www.vis.com.tw/
Download Datasheet Parametric View All

VP464641641BTGC-10 Overview

Synchronous DRAM Module, 4MX64, 7ns, CMOS, SODIMM-144

VP464641641BTGC-10 Parametric

Parameter NameAttribute value
Parts packaging codeMODULE
package instructionDIMM,
Contacts144
Reach Compliance Codeunknown
ECCN codeEAR99
access modeSINGLE BANK PAGE BURST
Maximum access time7 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-XDMA-N144
memory density268435456 bit
Memory IC TypeSYNCHRONOUS DRAM MODULE
memory width64
Number of functions1
Number of ports1
Number of terminals144
word count4194304 words
character code4000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize4MX64
Package body materialUNSPECIFIED
encapsulated codeDIMM
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Certification statusNot Qualified
self refreshYES
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal locationDUAL
Base Number Matches1
VIS
Description
Preliminary
VP464641641B,VP864641641B
4M, 8MX64-Bit
SDRAM SODIMM Module
The VP464641641B and VP864641641B are 4Mx64-bit and 8Mx64-bit small-outline dual-in-line syn-
chronous dynamic RAM module (SODIMM). It is mounted with 4/8 pieces of 4Mx16 synchronous DRAM
(VG36641641BT), and each in a standard 54 pin TSOP package. Decoupling capacitors are mounted on
power supply line for noise reduction. The module use serial presence detects implemented via a 2k-bit
EEPROM component.
Features
VP464641641B, VP864641641B :
• Comply to Intel pc 100 spuitication
• Single 3.3V (
±
0.3V
) power supply
• Utilizes -8H, -8L, -10 SDRAM components
• 32MB (VP464641641B) and 64MB (VP864641641B)
• Fully synchronous with all signals referenced to a positive clock edge
• Nonbuffered
• Programmable burst length (1,2,4,8 & Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• I/O level : LVTTL interface
• Random column access in every cycle
• 4096 refresh cycles/64ms
• Serial Presence Detect (SPD)
• JEDEC Standard pinout
• Performance Options (at 100MHz)
Marking
-8H
-8L
-10
unit: clock
SDRAMs
-8H
-8L
-10
CL
2
3
3
T
RCD
2
2
3
T
RP
2
2
3
T
RC
7
7
8
Document:1G5-0122
Rev.2
Page 1

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