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CY38100V256B-83BBC

Description
Loadable PLD, 15ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FBGA-256
CategoryProgrammable logic devices    Programmable logic   
File Size946KB,32 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

CY38100V256B-83BBC Overview

Loadable PLD, 15ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, FBGA-256

CY38100V256B-83BBC Parametric

Parameter NameAttribute value
Parts packaging codeBGA
package instructionLBGA,
Contacts256
Reach Compliance Codeunknown
Other featuresIT CAN ALSO HAVE AN INPUT VOLTAGE OF 3.3V
JESD-30 codeS-PBGA-B256
length17 mm
Number of I/O lines180
Number of terminals256
Maximum operating temperature70 °C
Minimum operating temperature
organize180 I/O
Output functionMACROCELL
Package body materialPLASTIC/EPOXY
encapsulated codeLBGA
Package shapeSQUARE
Package formGRID ARRAY, LOW PROFILE
Programmable logic typeLOADABLE PLD
propagation delay15 ns
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage2.7 V
Minimum supply voltage2.3 V
Nominal supply voltage2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
width17 mm
Base Number Matches1
PRELIMINARY
Quantum38K™ ISR™
CPLD Family
CPLDs at ASIC Prices™
Features
• High density
— 30K to 100K usable gates
— 512 to 1536 macrocells
— 136 to 302 maximum I/O pins
— 8 Dedicated Inputs including 4 clock pins and 4
global I/O control signal pins; 4 JTAG interface pins
for reconfigurability/boundary scan
• Embedded Memory
— 16K to 48K bits embedded dual-port Channel mem-
ory
• 125 MHz in-system operation
• AnyVolt™ interface
— 3.3V and 2.5V V
CC
operation
— 3.3V, 2.5V and 1.8V I/O capability
• Low Power Operation
0.18-µm 6-layer metal SRAM-based logic process
— Full-CMOS implementation of product term array
• Simple timing model
— No penalty for using full 16 product terms / macrocell
— No delay for single product term steering or sharing
• Flexible clocking
— 4 synchronous clocks per device
— Locally generated Product Term clock
— Clock polarity control at each register
• Carry-chain logic for fast and efficient arithmetic oper-
ations
• Multiple I/O standards supported:
— LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI
• Compatible with NOBL™, ZBT™, and QDR™ SRAMs
• Programmable slew rate control on each I/O pin
• User-Programmable Bus Hold capability on each I/O pin
• Fully PCI compliant (as per PCI spec rev. 2.2)
• Compact PCI hot swap ready
• Multiple package/pinout offering across all densities
— 208 to 484 pins in PQFP and FBGA packages
— Simplifies design migration across density
• In-System Reprogrammable™ (ISR™)
— JTAG-compliant on-board configuration
— Design changes don’t cause pinout changes
• IEEE1149.1 JTAG boundary scan
• Pin-to-pin compatible with Cypress’s high-end
Delta39K CPLDs
Development Software
Warp®
— IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
— Active-HDL FSM graphical finite state machine editor
— Active-HDL SIM post-synthesis timing simulator
— Architecture Explorer for detailed design analysis
— Static Timing Analyzer for critical path analysis
— Available on Windows 95™, Windows 98™ & Win-
dows NT™ for $99
— Supports all Cypress programmable logic products
Quantum38K™ ISR CPLD Family Members
Channel
memory
(Kbits)
16
24
48
Maximum
I/O Pins
176
218
302
f
MAX2
(MHz)
125
125
125
Speed — t
PD
Pin-to-Pin
(ns)
10
10
10
Standby I
CC
[2]
T
A
=25°C
3.3/2.5V
10 mA
10 mA
10 mA
Device
38K30
38K50
38K100
Typical Gates
[1]
16K–48K
23K–72K
46K–144K
Macrocells
512
768
1536
Note:
1. Upper limit of typical gates is calculated by assuming only 50% of the channel memory is used.
2. Standby I
CC
values are with no output load and stable inputs.
Cypress Semiconductor Corporation
Document #: 38-03043 Rev. *A
3901 North First Street
San Jose
CA 95134
• 408-943-2600
Revised July 5, 2001
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