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DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µ
PC324
LOW POWER QUAD OPERATIONAL AMPLIFIER
DESCRIPTION
The
µ
PC324 is a quad operational amplifier which is
designed to operate from a single power supply over a
wide range of voltages.
Operation from split power
supplies is also possible and the power supply current
drain is very low. Further advantage, the input common-
mode voltage can also swing to ground in the linear
mode.
FEATURES
• Internal frequency compensation
• Wide output voltage swing V
–
to V
+
–1.5 V
• Common Mode input voltage range includes V
–
• Wide supply range
3 V to 30 V (Single)
±1.5
V to
±15
V (Split)
• Output short circuit protection
EQUIVALENT CIRCUIT (1/4 Circuit)
100
µ
A
6
µ
A
Q
2
Q
3
6
µ
A
Q
5
I
I
I
N
Q
10
Q
8
Q
9
Q
12
50
µ
A
V
–
Q
1
Q
4
C
C
Q
7
R
SC
Q
11
OUTPUT
Q
13
Q
6
PIN CONFIGURATION (Top View)
µ
PC324C, 324G2
OUT1 1
I
I1
2
I
N1
3
V
+
4
I
N2
5
I
I2
6
OUT2 7
–+
2
+–
3
1
–+
4
+–
V
+
14 OUT4
13 I
I4
12 I
N4
11 V
–
10 I
N3
9 I
I3
8 OUT3
ORDERING INFORMATION
Part Number
Package
14-pin plastic DIP (7.62 mm (300))
14-pin plastic SOP (5.72 mm (225))
14-pin plastic SOP (5.72 mm (225))
µ
PC324C
µ
PC324G2
µ
PC324G2(5)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. G11763EJ4V0DS00 (4th edition)
Date Published March 2004 N (CP)K
Printed in Japan
The mark
shows major revised points.
c
µ
PC324
ABSOLUTE MAXIMUM RATINGS (T
A
= 25
°
C)
Parameter
Voltage between V
+
and V
–
Differential Input Voltage
Input Voltage
Output Voltage
Power Dissipation
C Package
Note 2
Note 3
Note 4
Note 1
Symbol
V
+
–V
–
V
ID
V
I
V
O
P
T
Ratings
–0.3 to +32
±32
V
–
–0.3 to V
–
+32
V
–
–0.3 to V
+
+0.3
570
550
Indefinite
T
A
T
stg
–20 to +80
–55 to + 125
Unit
V
V
V
V
mW
mW
sec
°C
°C
G2 Package
Note 5
Output Short Circuit Duration
Operating Ambient Temperature
Storage Temperature
Note 6
Notes 1.
Reverse connection of supply voltage can cause destruction.
2.
The input voltage should be allowed to input without damage or destruction independent of the
magnitude of V
+
. Either input signal should not be allowed to go negative by more than 0.3 V. The normal
operation will establish when the both inputs are within the Common Mode Input Voltage Range of
electrical characteristics.
3.
This specification is the voltage which should be allowed to supply to the output terminal from external
without damage or destructive. Even during the transition period of supply voltage, power on/off etc.,
this specification should be kept. The output voltage of normal operation will be the Output Voltage Swing
of electrical characteristics.
4.
Thermal derating factor is –7.6 mW/°C when operating ambient temperature is higher than 50
°C.
5.
Thermal derating factor is –5.5 mW/°C when operating ambient temperature is higher than 25
°C.
6.
Pay careful attention to the total power dissipation not to exceed the absolute maximum ratings, Note
4 and Note 5.
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage (Split)
Supply Voltage (V = GND)
–
Symbol
V
±
V
+
MIN.
±1.5
3
TYP.
MAX.
±15
30
Unit
V
V
µ
PC324C,
µ
PC324G2
ELECTRICAL CHARACTERISTICS (T
A
= 25
°
C, V
+
= 5 V, V
–
= GND)
Parameter
Input Offset Voltage
Input Offset Current
Input Bias Current
Note 7
Symbol
V
IO
I
IO
I
B
A
V
I
CC
CMR
SVR
V
O
V
ICM
I
O SOURCE
I
O SINK
V
IN +
= +1 V, V
IN–
= 0 V
V
IN –
= +1 V, V
IN+
= 0 V
V
IN–
= +1 V, V
IN+
= 0 V, V
O
= 200 mV
Channel Separation
f = 1 kHz to 20 kHz
R
L
= 2 kΩ (Connect to GND)
R
L
≥
2 kΩ
R
L
=
∞,
I
O
= 0 A
65
65
0
0
20
10
12
40
20
50
120
25
R
S
= 0
Ω
Conditions
MIN.
TYP.
±2
±5
45
100
1.0
85
100
V
+
– 1.5
V
+
– 1.5
2
MAX.
±7
±50
250
Unit
mV
nA
nA
V/mV
mA
dB
dB
V
V
mA
mA
Large Single Voltage Gain
Supply Current
Note 8
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Output Voltage Swing
Common Mode Input Voltage Range
Output Current (SOURCE)
Output Current (SINK)
µ
A
dB
Notes 7.
Input bias currents flow out from IC. Because each currents are base current of PNP-transistor on input
stage.
8.
This current flows irrespective of the existence of use.
2
Data Sheet G11763EJ4V0DS
FPGA/CPLD
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