SCN68562C4A52 datasheet, PDF - EEWORLD Datasheet

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SCN68562C4A52: DescriptionMicro Peripheral IC, MOS, PQCC52; CategoryThe embedded processor and controller Microcontrollers and processors; File Size120KB，18 Pages; ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.); Websitehttps://www.nxp.com/

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SCN68562C4A52 Overview

Micro Peripheral IC, MOS, PQCC52

SCN68562C4A52 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	QCCJ, LDCC52,.8SQ
Reach Compliance Code	unknown
JESD-30 code	S-PQCC-J52
JESD-609 code	e0
Number of terminals	52
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC52,.8SQ
Package shape	SQUARE
Package form	CHIP CARRIER
power supply	5 V
Certification status	Not Qualified
Maximum slew rate	275 mA
Nominal supply voltage	5 V
surface mount	YES
technology	MOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Base Number Matches	1

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INTEGRATED CIRCUITS

SCN68562

Dual universal serial communications

controller (DUSCC)

Product specification

IC19 Data Handbook

1995 May 01

Philips

Semiconductors

Philips Semiconductors

Product specification

Dual universal serial communications controller (DUSCC)

SCN68562

PIN DESCRIPTION

In this data sheet, signals are discussed using the terms ‘active’ and ‘inactive’ or ‘asserted’ and ‘negated’ independent of whether the signal is

active in the High (logic 1) or Low (logic 0) state. N at the end of a pin name signifies the signal associated with the pin is active-Low (see

individual pin description for the definition of the active level of each signal.) Pins which are provided for both channels are designated by A/B

after the name of the pin and the active-Low state indicator, N, if applicable. A similar method is used for registers provided for both channels:

these are designated by either an underline or by A/B after the name.

MNEMONIC

A1 – A6

D0 – D7

DIP

PIN NO.

4-2,

45-47

31-28,

21-18

TYPE

I/O

NAME AND FUNCTION

Address Lines:

Active-High. Address inputs which specify which of the internal registers

is accessed for read/write operation.

Bidirectional Data Bus:

Active High, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All

data, command, and status transfers between the CPU and the DUSCC take place over

this bus. The data bus is enabled when CSN is Low, during interrupt acknowledge cycles

and single-address DMA acknowledge cycles.

Read/Write:

A High input indicates a read cycle and a Low input indicates a write cycle

when a cycle is initiated by assertion of the CSN input.

Chip Select:

Active-Low input. When Low, data transfers between the CPU and the

DUSCC are enabled on D0 – D7 as controlled by the R/WN and A1 – A6 inputs. When

CSN is High, the DUSCC is isolated from the data bus (except during interrupt

acknowledge cycles and single-address DMA transfers) and D0 – D7 are placed in the

3-State condition.

Data Transfer Acknowledge:

Active-Low, 3-State. DTACKN is asserted on a write cycle

to indicate that the data on the bus has been latched, and on a read cycle or interrupt

acknowledge cycle to indicate valid data is on the bus. The signal is negated when

completion of the cycle is indicated by negation of the CSN or IACKN input, and returns to

the inactive state (3-State) a short period after it is negated. In a single address DMA

mode, data is latched with the falling edge of DTCN. DTACKN is negated when

completion of the cycle is indicated by the assertion of DTCN or negation of DMA

acknowledge inputs (whichever occurs first), and returns to the inactive state (3-State) a

short period after it is negated. When negated, DTACKN becomes an open-drain output

and requires an external pull-up resistor.

Interrupt Request:

Active-Low, open-drain. This output is asserted upon occurrence of

any enabled interrupting condition. The CPU can read the general status register to

determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle

to cause the DUSCC to output an interrupt vector on the data bus.

Interrupt Acknowledge:

Active-Low. When IACKN is asserted, the DUSCC responds by

placing the contents of the interrupt vector register (modified or unmodified by status) on

the data bus and asserting DTACKN. If no active interrupt is pending, DTACKN is not

asserted.

Crystal or External Clock:

When using the crystal oscillator, the crystal is connected

between pins X1 and X2. If a crystal is not used, and external clock is supplied at this

input. This clock is used to drive the internal bit rate generator, as an optional input to the

counter/timer or DPLL, and to provide other required clocking signals.

Crystal or Interrupt Daisy Chain:

When a crystal is used as the timing source, the

crystal is connected between pins X1 and X2. This pin can be programmed to provide and

interrupt daisy chain active-Low output which propagates the IACKN signal to lower priority

devices, if no active interrupt is pending. This pin should be grounded when an external

clock is used on X1 and X2, is not used as an interrupt daisy chain output.

Master Reset:

Active-Low. A low on this pin resets the transmitters and receivers and

resets the registers shown in Table 1 of the CDUSCC Users’ Guide. Reset in

asynchronous, i.e., no clock is required.

Channel A (B) Receiver Serial Data Input:

The least significant bit is received first. If

external receiver clock is specified for the channel, the input is sampled on the rising edge

of the clock.

Channel A (B) Transmitter Serial Data Output:

The least significant bit is transmitted

first. This output is held in the marking (High) condition when the transmitter is disabled or

when the channel is operating in local loopback mode. If external transmitter clock is

specified for the channel, the data is shifted on the falling edge of the clock.

Channel A (B) Receiver/Transmitter Clock:

As an input, it can be programmed to

supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, can supply the

counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock (1X).

The maximum external receiver/transmitter clock frequency is 4MHz.

R/WN

CSN

DTACKN

IRQN

IACKN

X1/CLK

X2/IDCN

RESETN

RxDA, RxDB

37, 12

TxDA, TxDB

36, 13

RTxCA, RTxCB

39, 10

I/O

1995 May 01

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