MA007A
3-in-1 8-bit serial to parallel latch
Features
•
Three 8-bit serial input
•
Three 8-bit parallel output
•
Operation voltage: 2.0V to 5.7V
•
Storage register with 3-state outputs
•
Shift register with direct clear
Selection Information
Package / Dice
Parallel Output
Sink Current
MA007AH
Dice
MA007AP
44-PLCC
•
5 MHz (typical) shift out frequency
•
Output capability:
♦
Parallel outputs; bus driver
♦
Serial output; standard
MA007AD
48-LQFP
24 pins
20mA
MA007AF
44-PQFP
Application Field
Serial-to-parallel data conversion
Remote control holding register
This document contains information on a new product under development by MEGAWIN. MEGAWIN reserves the right to change or discontinue
this product without notice.
©
MEGAWIN Technology Co., Ltd. 2006 All rights reserved.
2005/11 version A1
MEGAWIN
General Description
The MA007 are high-speed Si-gate CMOS
devices. There are three groups 8-stage serial
shift register with a storage register and 3-state
outputs in MA007. The shift register and storage
register have separate clocks. Data is shifted on
the positive-going transitions of the SCLK input.
The data in each register is transferred to the
storage register on a positive-going transition of
the PCLK input. If both clocks are connected
together, the shift register will always be one clock
pulse ahead of the storage register. The shift
register has a serial input (D
INx
) and a serial
standard output (D
OUTx
) for cascading. It is also
provided with asynchronous reset (active LOW)
for all 8 stages shift register. The storage register
has 8 parallel 3-state bus driver outputs. Data in
the storage register appears at the output
whenever the output enable input (/OE) is LOW.
Pad Description
Pad No.
1
2
3
4
5, 6, 7
10, 9, 8
20 to 13
29 to 22
38 to 31
Pad Name
/OE
PCLK
/SCLR
SCLK
D
IN0
, D
IN1
, D
IN2
D
OUT0
, D
OUT1
, D
OUT2
Q
20
to Q
27
Q
10
to Q
17
Q
00
to Q
07
V
CC
GND
12, 30, 40
11, 21, 39, 41
I/O
I
I
I
I
I
O
O
O
O
P
P
Description
Output enable (active LOW)
Parallel register clock input
Serial register reset (active LOW)
Shift register clock input
Serial data input
Serial data output
Parallel data group 2 output
Parallel data group 1 output
Parallel data group 0 output
Positive supply voltage
Power ground (0 V)
2
MA007A Technical Summary
MEGAWIN
Block Diagram
5
Din0
6
Din1
7
Din2
4
3
2
1
SCLK
/SCLR
PCLK
/OE
8-STAGE SHIFT
REGISTER
8-STAGE SHIFT
REGISTER
8-STAGE SHIFT
REGISTER
Dout0 10
Dout1 9
Dout2 8
8-BIT STORAGE
REGISTER
8-BIT STORAGE
REGISTER
8-BIT STORAGE
REGISTER
3-STATE OUTPUTS
3-STATE OUTPUTS
3-STATE OUTPUTS
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
Q00
Q01
Q02
Q03
Q04
Q05
Q06
Q07
Q20
Q21
Q22
Q23
Q24
Q25
Q26
Q27
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
38
13
14
15
16
17
18
19
20
MEGAWIN
MA007A Technical Summary
3
Function Description
FUNCTION TABLE
INPUTS
SCLK PCLK /OE /SCLR D
INx
X
X
X
X
↑
X
L
L
H
L
L
L
X
X
X
OUTPUTS
FUNCTON
D
OUTx
L
L
L
Q
xN
NC
L
Z
A LOW level on /SCLR only affects the shift registers
Empty shift register loaded into storage register
Shift register clear. Parallel outputs in high-impedance
OFF-state
Logic high level shifted into shift register stage 0.
Contents of all shift register stages shifted through, e.g.
previous state of stage 6 (internal Qx6’) appears on the
serial output (D
OUTx
)
Contents of shift register stages (internal Qxn’) are
transferred to the storage register and parallel output
stages
Contents of shift register shifted through. Previous
contents of the shift register are transferred to the
storage register and the parallel output stages.
↑
X
L
H
H
Qx6’
NC
X
↑
L
H
X
NC
Qxn’
↑
↑
L
H
X
Qx6’
Qxn’
Notes
H = HIGH voltage level; L = LOW voltage level
↑
= LOW-to-HIGH transition;
↓
= HIGH-to-LOW
Z = high-impedance OFF-state; NC = no change
X = don’t care.
4
MA007A Technical Summary
MEGAWIN
Application Circuit
1
2
3
4
5
VCC
6
D
VCC
VCC
D
R7
V+ (Ext)
VCC
1K
Q7
8550D
R8
1K
Q8
8550D
Label_C1
+ C2
470uF
C3
0.1uF
VCC
SPK1
VCC
8 Ohm
SPK1
C
U1
MLC031A/021A/017A_COB
R3
620
Q2
8050S
U2
1
2
3
4
5
6
7
8
9
10
VCC
C11
0.1uF
0.1uF
11
12
13
14
15
16
17
18
19
20
OE
PCLK
SCLR
SCLK
Din0
Din1
Din2
Dout2
Dout1
Dout0
GND
VCC
Q27
Q26
Q25
Q24
Q23
Q22
Q21
Q20
GND
OPT
VCC
GND
Q00
Q01
Q02
Q03
Q04
Q05
Q06
Q07
VCC
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
GND
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
C12
0.1uF
R10
R11
R12
R13
R14
R15
R16
R17
R20
R21
R22
R23
R24
R25
R26
R27
100 * 8
VCC
LED
LED
LED
LED
P1.0
R5
1K
Q5
8550D
P1.1
R6
1K
VCC
Label_C2
Q6
8550D
C
VCC
IC_VCC
D6
1N4148
Li-Battery
3.0V
R1
680K
@4MHz
D5
IC_VCC
1N60P
C8
0.1uF
1
2
3
4
5
6
7
8
9
VDD
OSCO
OSCI
GND
RES
TEST
X32O
X32I
P0.0
SPK2
AVDD
SPK1
AGND
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
36
35
34
33
32
31
30
29
28
27
C9
SPK1
C4
47uF
B
C5
100pF
R2
8.2K
X1
Q1
8050S
32.768KHz
C6
20pF
C7
20pF
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P1.0
P1.1
100 * 8
Label_C1
R30
R31
R32
R33
R34
R35
R36
R37
100 * 8
LED
LED
Label_C2
B
MA007A_COB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A
Title
Size
B
Date:
File:
1
2
3
4
5
28-Mar-2005
Sheet of
E:\User\Feng\Project\DataSheet\MA007A\LED_Clock_ASIC2_AP.DDB
Drawn By:
6
Number
Revision
P1.0
P1.1
A
MEGAWIN
MA007A Technical Summary
5
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