FUJITSU MICROELECTRONICS
DATA SHEET
DS07-16310-2E
32-Bit Microcontroller
CMOS
FR30 Series
MB91F127/F128
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DESCRIPTION
This model, designed on the basis of 32-bit RISC CPU (FR30 series), is a standard single-chip micro controller
with built-in I/O resources and bus control functions. The functions are suitable for built-in control that requires
high-speed CPU processing.
MB91F127 includes 256 Kbytes built-in flash memory and 14 Kbytes built-in RAM. MB91F128 includes 510 Kbytes
built-in flash memory and 14 Kbytes built-in RAM.
The specifications of the devices are best suited for applications requiring high-level CPU processing capabilities,
such as navigation system, high-performance FAX, and printer controller.
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FEATURES
FR-CPU
• 32-bit RISC (FR30), load/store architecture, 5-step pipeline
• Operating frequency : Internal 25 MHz
• General register : 32bit x 16 registers
• 16-bit fixed-length instructions (primitives), 1 instruction/1 cycle
• Instructions of memory-to-memory transfer, bit processing, and barrel shift : Instructions suitable for built-in
control
• Function entry/exit instructions, multi load/store instruction for register data : High-level language compatible
instructions
• Register interlock functions : Simple description of assembler language
• Branch instructions with delay slot : Reduced overhead on branching process
(Continued)
• Built-in multiplier/ Supporting at instruction level
Signed 32-bit multiplying : 5 cycles
Signed 16-bit multiplying : 3 cycles
• Interrupt (saving PC and PS) : 6 cycles, 16 priority levels
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2002-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2008.11
MB91F127/F128
Bus interface
• Maximum of 25 MHz internal operation rate
• 25-bit address bus (32 MB space)
• 16-bit address output, 8/16-bit data input/output
• Basic bus cycle : 2-clock cycle
• Chip selection outputs specifiable in a minimum of 64 Kbytes steps : 6 outputs
• Automatic wait cycle : Specifiable flexibly from 0 cycle to 7 cycles for each area
• Supporting time-division input/output interface for address/data (for area 1 only)
• Unassigned data/address terminals are available as input/output ports
• Supporting little endian mode (selecting one area from area 1 to area 5)
DMAC (DMA controller)
• 8 channels
• Transfer factor : Interrupt request of built-in resources
• Transfer sequence : Step transfer/Block transfer/Burst transfer/Consecutive transfer
• Transfer data length : Selectable among 8 bits, 16 bits, and 32 bits
• Pausing is allowed by interrupt request
UART
• 3 channels
• Full-duplex double buffer
• Data length : 7 to 9 bits (no parity), 6 to 8 bits (with parity)
• Asynchronous (start-stop synchronization) or CLK synchronous communication is selectable
• Multi processor mode
• Built-in 16-bit timer (U-Timer) used as a baud-rate generator : Generates an arbitrary baud rate
• External clock is available as a transfer clock
• Error detection : parity, frame, and overrun
A/D converter (sequential transducer)
• 8/10-bit resolution, 8 channels
• Sequential comparison and transducer : At 25 MHz, 5.2
µs
• Built-in sample and hold circuit
• Conversion mode : Selectable among single conversion, scan conversion, and repeat conversion
• Activation : Selectable among software, external trigger, and built-in timer
Reload timer
• 16-bit timer : 3 channels
• Internal clock : 2-clock cycle resolution, selectable among 2/8/32 dividing and external clock
Other interval timers
• 16-bit timer : 3 channels (U-Timer)
• PPG timer : 4 channels
• 16-bit OCU : 4 channels, ICU : 4 channels, Free-run timer : 1 channel
• Watchdog timer: 1 channel
Flash memory 510 KB
• 510 KB FLASH ROM: Read/Write/Erase is allowed with a same power
(Continued)
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DS07-16310-2E
MB91F127/F128
(Continued)
Built- in RAM 14 KB
• D-bus RAM 12 KB, C-bus RAM 2 KB
Bit search module
• Position of a first bit that changes between “1” and “0” is searched in one cycle, within an MSB of one word.
Interrupt controller
• External interrupt input : Normal interrupt×6 (INT0 to INT5)
• Internal interrupt factors : UART, DMAC, A/D, Reload timer, UTIMER, delay interrupt, PPG, ICU, and OCU
• Priority levels are programmable (16 levels)
Reset factors
• Power-on reset/watchdog timer/software reset/external reset
Low power consumption mode
• Sleep/stop mode
Clock control
• Built-in PLL circuit, selectable among 1-multiplication, and 2-multiplication
• Gearing function : Operation clock frequencies are freely and independently specifiable for CPU and
peripherals.
Gear clocks are selectable among 1/1, 1/2, 1/4, and 1/8 (or among 1/2, 1/4, 1/8, and 1/16).
Upper limit of peripheral operations is 25 MHz.
Others
• Package : LQFP-100
• CMOS technology : 0.35
µm
• Power supply voltage : 3.3 V±0.3 V
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SERIES CONFIGURATION
Model name
Outline
FLASH memory
D-bus RAM
C-bus RAM
MB91F127
Quantity production
256 KB
12 KB
2 KB
MB91F128
Quantity production
510 KB
12 KB
2 KB
MB91FV129
Evaluation product
510 KB
16 KB
2 KB
DS07-16310-2E
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MB91F127/F128
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PIN ASSIGNMENT
(TOP VIEW)
4
P21/D17
P22/D18
P23/D19
P24/D20
P25/D21
P26/D22
P27/D23
P30/D24
P31/D25
P32/D26
P33/D27
P34/D28
P35/D29
P36/D30
VSS
P37/D31
P40/A00
VCC
P41/A01
P42/A02
P43/A03
P44/A04
P45/A05
P46/A06
P47/A07
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PG5/OC1
PG6/OC2
PG7/OC3
VCC
PA6/CLK
PA5/CS5/SC1
PA4/CS4/SI1
PA3/CS3/SO1
PA2/CS2
PA1/CS1
PA0/CS0
P86/ALE
HST
RST
VSS
MD0
MD1
MD2
P80/RDY
P81/BGRNT/IN0
P82/BRQ/IN1
P83/RD
P84/WR0
P85/WR1
P20/D16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PG4/OC0
PG3/OCPA3
PG2/OCPA2
PG1/OCPA1
PG0/OCPA0
PE0/INT0
PE1/INT1
VCC
X0
X1
VSS
PE2/INT2
PE3/INT3
PE4/INT4/TCI1
PE5/INT5/SC0
PE6/SI0
PE7/SO0
PF3/SC2/ATG
PF2/SO2
PF1/SI2
PF0/TCI0
PJ7/AN7
PJ6/AN6
PJ5/AN5
PJ4/AN4
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PJ3/AN3
PJ2/AN2
PJ1/AN1
PJ0/AN0
AVSS/AVRL
AVRH
AVCC
P70/A24/FRCK/TCI2
P67/A23/IN3
P66/A22/IN2
VSS
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A09
P50/A08
(FPT-100P-M05)
DS07-16310-2E
MB91F127/F128
■
PIN DESCRIPTION
Note that the numbers in the table are not pin numbers on a package.
Input/output
No.
Pin name
Description
circuit type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
D16/P20
D17/P21
D18/P22
D19/P23
D20/P24
D21/P25
D22/P26
D23/P27
D24/P30
D25/P31
D26/P32
D27/P33
D28/P34
D29/P35
D30/P36
D31/P37
A00/P40
A01/P41
A02/P42
A03/P43
A04/P44
A05/P45
A06/P46
A07/P47
A08/P50
A09/P51
A10/P52
A11/P53
A12/P54
A13/P55
A14/P56
A15/P57
A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66/IN2
A23/P67/IN3
D
Bit 16 through bit 23 of external data bus.
The terminals are available as general I/O ports (P20 through
P27) when external bus width is specified at 8 bits or in single-
chip mode.
D
Bit 24 through bit 31 of external data bus.
The terminals are available as general I/O ports (P30 through
P37) when the terminals are not used.
D
Bit 00 through bit 15 of external address bus.
The terminals are available as general I/O ports (P40 through
P47 and P50 through P57) when the terminals are not used as
address buses.
D
Bit 16 through bit 23 of external address bus.
The terminals are available as general I/O ports (P60 through
P67) when the terminals are not used as address busses.
[IN2,IN3]: Input terminals of input capture.
This function is active when input capture is operating.
(Continued)
DS07-16310-2E
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