ACT–SF128K16 High Speed
128Kx16 SRAM/FLASH Multichip Module
CIRCUIT TECHNOLOGY
FEATURES
www.aeroflex.com
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Packaging – Hermetic Ceramic
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2 – 128K x 8 SRAMs & 2 – 128K x 8 Flash Die in
One MCM
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Access Times of 25ns (SRAM) and 60ns (Flash)
or
35ns (SRAM) and 70 or 90ns (Flash)
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128K x 16 SRAM
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128K x 16 5V Flash
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Organized as 128K x 16 of SRAM and 128K x 16 of
Flash Memory with Separate Data Buses
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Both Blocks of Memory are User Configurable as
256K x 8
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Low Power CMOS
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Input and Output TTL Compatible Design
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MIL-PRF-38534 Compliant MCMs Available
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Decoupling Capacitors and Multiple Grounds for Low
Noise
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Industrial and Military Temperature Ranges
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Industry Standard Pinouts
Note: Programming information available upon request
66 Pin, 1.08" x 1.08" x .160" PGA Type, No Shoulder,
Aeroflex code# "P3"
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66 Pin, 1.08" x 1.08" x .185" PGA Type, With
Shoulder, Aeroflex code# "P7"
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68 Lead, .94" x .94" x .140" Single-Cavity Small
Outline Gull Wing, Aeroflex code# "F18"
(Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)
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DESC SMD Pending – 5962-96900
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FLASH MEMORY FEATURES
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Sector Architecture (Each Die)
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Equal Sectors of 16K bytes each
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Any combination of sectors can be erased with one
command sequence.
+5V Programing, 5V ±10% Supply
Embedded Erase and Program Algorithms
Hardware and Software Write Protection
Internal Program Control Time.
10,000 Erase/Program Cycles
q
8
Block Diagram – PGA Type Package (P3,P7) and CQFP (F18)
Pin Description
SWE
1
SCE
1
SWE
2
SCE
2
FWE
1
FCE
1
FWE
2
FCE
2
FI/O
0-15
OE
A
0
–
A
16
128Kx8
SRAM
8
SI/O
0-7
128Kx8
SRAM
8
SI/O
8-15
128Kx8
Flash
8
FI/O
0-7
128Kx8
Flash
8
FI/O
8-15
SI/O
0-15
A
0–16
FWE
1-2
Flash Data I/O
SRAM Data I/O
Address Inputs
Flash Write Enables
SWE
1-2
SRAM Write Enables
FCE
1-2
SCE
1-2
OE
NC
V
CC
GND
Flash Chip Enables
SRAM Chip Enables
Output Enable
Not Connected
Power Supply
Ground
eroflex Circuit Technology - Advanced Multichip Modules © SCD1677 REV A 4/28/98
Absolute Maximum Ratings
Symbol
T
C
T
STG
V
G
T
L
Parameter
Flash Data Retention
Flash Endurance (Write/Erase Cycles)
10 Years
10,000
Rating
Case Operating Temperature
Storage Temperature
Maximum Signal Voltage to Ground
Maximum Lead Temperature (10 seconds)
Range
-55 to +125
-65 to +150
-0.5 to +7
300
Units
°C
°C
V
°C
Normal Operating Conditions
Symbol
V
CC
V
IH
V
IL
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Minimum
+4.5
+2.2
-0.5
Maximum
+5.5
V
CC
+ 0.3
+0.8
Units
V
V
V
Capacitance
(
V
IN
= 0V, f = 1MHz, T
C
= 25°C
)
Symbol
C
AD
C
OE
F/S C
WE
1,2
F/S C
CE
1,2
F/S C
I
/
O
Parameter
A
0
–
A
16
Capacitance
OE Capacitance
F/S Write Enable Capacitance
F/S Chip Enable Capacitance
I/O
0
– I/O
15
Capacitance
Maximum
50
50
20
20
20
Units
pF
pF
pF
pF
pF
These parameters are guaranteed by design but not tested
DC Characteristics
(V
CC
= 5.0V, V
SS
= 0V, T
C
= -55°C to +125°C, unless otherwise indicated)
Parameter
Input Leakage Current
Output Leakage Current
Sym
I
LI
I
LO
Conditions
V
CC
= Max, V
IN
= 0 to V
CC
FCE = SCE = V
IH
, OE = V
IH,
V
OUT
= 0 to V
CC
SCE = V
IL
, OE = V
IH
, f = 5MHz, V
CC
=
Max, FCE = V
IH
FCE = SCE = V
IH
, OE = V
IH
, f = 5MHz,
V
CC
= Max
I
OL
= 8 mA, V
CC
= 4.5V
I
OH
= -4.0 mA, , V
CC
= 4.5V
FCE = V
IL
, OE = V
IH
, SCE = V
IH
FCE = V
IL
, OE = V
IH
, SCE = V
IH
I
OL
= 12 mA, V
CC
= 4.5V, SCE = V
IH
Min
Max Units
10
10
250
40
0.4
µA
µA
mA
mA
V
V
100
130
0.45
mA
mA
V
V
V
SRAM Operating Supply Current x 16 Mode I
CC
x16
Standby Current
SRAM Output Low Voltage
SRAM Output High Voltage
Flash Vcc Active Current for Read (1)
Flash Vcc Active Current for Program or
Erase (2)
Flash Output Low Voltage
Flash Output High Voltage
Flash Low Vcc Lock Out Voltage
I
SB
V
OL
V
OH
I
CC1
I
CC2
V
OL
V
OH
V
LKO
2.4
I
OH
= -2.5 mA, , V
CC
= 4.5V, SCE = V
IH
0.85 x V
CC
3.2
Notes: 1) The I
CC
current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The frequency component typically is less
than 2mA/MHz, with OE at V
IH
2) I
CC
active while Embedded Algorithim (program or erase) is in progress 3) DC test conditions: V
IL
= 0.3V, V
IH
= V
CC
- 0.3V
Aeroflex Circuit Technology
2
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
SRAM AC Characteristics
(V
CC
= 5.0V, V
SS
= 0V, T
C
= -55°C to +125°C)
Read Cycle
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Output Enable to Output Valid
Chip Select to Output in Low Z *
Output Enable to Output in Low Z *
Chip Deselect to Output in High Z *
Output Disable to Output in High Z *
* Parameters guaranteed by design but not tested
Symbol
t
RC
t
AA
t
ACE
t
OH
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
3
0
12
12
0
15
3
0
20
20
–025
Min Max
25
25
25
0
20
–035
Min Max
35
35
35
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
Parameter
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Output Active from End of Write *
Write to Output in High Z *
Data Hold from Write Time
Address Hold Time
* Parameters guaranteed by design but not tested
Symbol
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
OW
t
WHZ
t
DH
t
AH
0
0
–025
Min Max
25
20
20
15
20
0
0
10
0
0
–035
Min Max
35
25
25
20
25
0
0
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SRAM Truth Table
Mode
Standby
Read
Output Disable
Write
SCE
H
L
L
L
OE
X
L
H
X
SWE
X
H
H
L
Data I/O
High Z
Data Out
High Z
Data In
Power
Standby
Active
Active
Active
Aeroflex Circuit Technology
3
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
Timing Diagrams — SRAM
Read Cycle Timing Diagrams
Read Cycle 1 (SCE = OE = V
IL
, SWE = V
IH
)
t
RC
A
0-18
t
AA
t
OH
D
I/O
Previous Data Valid
Data Valid
SCE
t
AS
SWE
S
EE
N
OTE
Write Cycle Timing Diagrams
Write Cycle (SWE Controlled, OE = V
IH
)
t
WC
A
0-18
t
AW
t
CW
t
AH
t
WP
t
WHZ
t
DW
Data Valid
t
DW
t
DH
D
I/O
Read Cycle 2 (SWE = V
IH
)
t
RC
A
0-18
t
AA
SCE
t
ACE
t
CLZ
S
EE
N
OTE
Write Cycle (SCE Controlled, OE = V
IH
)
t
WC
A
0-18
t
AW
t
CHZ
S
EE
N
OTE
t
AH
t
CW
t
AS
SCE
OE
t
WP
t
OE
t
OLZ
S
EE
N
OTE
t
OHZ
S
EE
N
OTE
SWE
t
DW
D
I/O
Data Valid
t
DH
D
I/O
High Z
Data Valid
UNDEFINED
DON’T CARE
Note: Guaranteed by design, but not tested.
AC Test Circuit
Current Source
I
OL
AC Test Conditions
Parameter
Typical
0 – 3.0
5
1.5
Units
V
ns
V
To Device Under Test
C
L
= 50 pF
V
Z
~ 1.5 V (Bipolar Supply)
Input Pulse Level
Input Rise and Fall
Input and Output Timing Reference Level
I
OH
Current Source
Notes:
1) V
Z
is programmable from -2V to +7V. 2) I
OL
and I
OH
programmable from 0 to 16 mA. 3) Tester Impedance
Z
O
= 75Ω.
4)
V
Z
is typically the midpoint of V
OH
and V
OL
. 5) I
OL
and I
OH
are adjusted to simulate a typical resistance
load circuit. 6) ATE Tester includes jig capacitance.
Aeroflex Circuit Technology
4
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
Flash AC Characteristics – Read Only Operations
(Vcc = 5.0V, Vss = 0V, T
C
= -55°C to +125°C)
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable to Output Valid
Chip Enable to Output High Z (1)
Output Enable High to Output High Z(1)
Output Hold from Address, CE or OE Change, Whichever is First
Note 1. Guaranteed by design, but not tested
Symbol
–60
–70
–90
Units
JEDEC Stand’d Min Max Min Max Min Max
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
t
RC
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
0
60
60
60
30
20
20
0
70
70
70
35
20
20
0
90
90
90
40
25
25
ns
ns
ns
ns
ns
ns
ns
Flash AC Characteristics – Write/Erase/Program Operations, FWE Controlled
(Vcc = 5.0V, Vss = 0V, T
C
= -55°C to +125°C)
Parameter
Write Cycle Time
Chip Enable Setup Time
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Enable Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation
Sector Erase Time
Chip Erase Time
Read Recovery Time before Write
Vcc Setup Time
Output Enable Setup Time
Output Enable Hold Time
1
Symbol
JEDEC Stand’d
t
AVAC
t
ELWL
t
WLWH
t
AVWL
t
DVWH
t
WHDX
t
WLAX
t
WHEH
t
WHWL
t
WHWH
1
t
WHWH
2
t
WHWH
3
t
GHWL
t
VCE
t
OES
t
OEH
t
WC
t
CE
t
WP
t
AS
t
DS
t
DH
t
AH
t
CH
t
WPH
–60
–70
–90
Min Max Min Max Min Max
60
0
30
0
30
0
45
0
20
14
TYP
60
120
0
50
12.5
10
10
0
50
12.5
10
70
0
35
0
30
0
45
0
20
14
TYP
60
120
0
50
12.5
90
0
45
0
45
0
45
0
20
14
TYP
60
120
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Sec
Sec
µs
µs
Sec
ns
Note: 1. For Toggle and Data Polling.
Flash AC Characteristics – Write/Erase/Program Operations, FCE Controlled
(Vcc = 5.0V, Vss = 0V, T
C
= -55°C to +125°C)
Parameter
Write Cycle Time
Write Enable Setup Time
Chip Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Hold from Write Enable High
Chip Enable Pulse Width High
Duration of Byte Programming
Sector Erase Time
Chip Erase Time
Read Recovery Time
Chip Programming Time
Symbol
JEDEC Stand’d
t
AVAC
t
WLE
L
t
ELEH
t
AVEL
t
DVEH
t
EHDX
t
ELAX
t
EHWH
t
EHEL
t
WHWH
1
t
WHWH
2
t
WHWH
3
t
WC
t
WS
t
CP
t
AS
t
DS
t
DH
t
AH
t
WH
t
CPH
–60
–70
–90
Min Max Min Max Min Max
60
0
35
0
30
0
45
0
20
14
TYP
60
120
0
12.5
0
12.5
70
0
35
0
30
0
45
0
20
14
TYP
60
120
0
12.5
90
0
50
0
50
0
50
0
20
14
TYP
60
120
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Sec
Sec
ns
Sec
t
GHEL
Aeroflex Circuit Technology
5
SCD1677 REV A 4/28/98 Plainview NY (516) 694-6700
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