ACT-SF41632 High Speed
128Kx32 SRAM / 512Kx32 Flash
Multichip Module
CIRCUIT TECHNOLOGY
FEATURES
4 – 128K x 8 SRAMs & 4 – 512K x 8 Flash Die in
One MCM
s
Access Times of 25ns, 35ns (SRAM) and
60ns, 70ns, 90ns (Flash)
s
Organized as 128K x 32 of SRAM and 512K x 32
of Flash Memory with Common Data Bus
s
Low Power CMOS
s
Input and Output TTL Compatible Design
s
MIL-PRF-38534 Compliant MCMs Available
s
Decoupling Capacitors and Multiple Grounds for
Low Noise
s
Commercial, Industrial and Military Temperature
Ranges
s
Industry Standard Pinouts
s
TTL Compatible Inputs and Outputs
s
Packaging – Hermetic Ceramic
q
66–Lead, PGA-Type, 1.385"SQ x 0.245"max,
Aeroflex code# "P1,P5 with/without shoulders)"
q
68–Lead, Dual-Cavity CQFP(F2), 0.88"SQ x
.20"max (.18 max thickness available, contact
factory for details)
(Drops into the 68 Lead
JEDEC .99"SQ CQFJ footprint)
s
s
www.aeroflex.com
FLASH MEMORY FEATURES
Sector Architecture (Each Die)
q
8 Equal Sectors of 64K bytes each
q
Any combination of sectors can be erased with
one command sequence.
s
+5V Programing, +5V Supply
s
Embedded Erase and Program Algorithms
s
Hardware and Software Write Protection
s
Page Program Operation and Internal Program
Control Time.
s
10,000 Erase/Program Cycles
A E
RO
F
LE
X
LA
B
S
I
NC
.
C
ISO
9001
E
RT
I
F
I
E
D
Block Diagram – PGA Type Package(P1 & P5) & CQFP(F2)
FWE
1
SWE
1
OE
A
0
–A
18
SCE
FCE
FWE
2
SWE
2
FWE
3
SWE
3
FWE
4
SWE
4
PIN DESCRIPTION
I/O
0-31
A
0–18
FWE
1-4
Data I/O
Address Inputs
Flash Write Enables
SWE
1-4
SRAM Write Enables
512K
X
8 F
LASH
128K
X
8 SRAM
512K
X
8 F
LASH
128K
X
8 SRAM
512K
X
8 F
LASH
128K
X
8 SRAM
512K
X
8 F
LASH
128K
X
8 SRAM
FCE
SCE
OE
NC
V
CC
GND
Flash Chip Enable
SRAM Chip Enable
Output Enable
Not Connected
Power Supply
Ground
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
eroflex Circuit Technology - Advanced Multichip Modules © SCD3851 REV A 5/21/98
Absolute Maximum Ratings
Symbol
T
C
T
STG
V
G
T
L
Parameter
Flash Data Retention
Flash Endurance (Write/Erase Cycles)
10 Years
10,000
Case Operating Temperature
Storage Temperature
Maximum Signal Voltage to Ground
Maximum Lead Temperature (10 seconds)
Rating
Range
-55 to +125
-65 to +150
-0.5 to +7
300
Units
°C
°C
V
°C
Normal Operating Conditions
Symbol
V
CC
V
IH
V
IL
Parameter
Power Supply Voltage
Input High Voltage
Input Low Voltage
Minimum
+4.5
+2.2
-0.5
Maximum
+5.5
V
CC
+ 0.3
+0.8
Units
V
V
V
Capacitance
(V
IN
= 0V, f = 1MHz, T
A
= 25°C
)
Symbol Parameter
C
AD
C
OE
C
WE
1-4
C
CE
C
I
/
O
A
0
–
A
18
Capacitance
OE Capacitance
F/S Write Enable Capacitance
F/S Chip Enable Capacitance
I/O
0
– I/O
31
Capacitance
Maximum
80
80
30
50
30
Units
pF
pF
pF
pF
pF
This parameter is guaranteed by design but not tested
DC Characteristics
(V
CC
= 5.0V, V
SS
= 0V, Tc = -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Sym
I
LI
I
LO
Conditions
V
CC
= Max, V
IN
= 0 to V
CC
FCE = SCE = V
IH
, OE = V
IH,
V
OUT
= 0 to V
CC
Min
Max Units
10
10
500
80
0.4
2.4
260
300
0.45
0.85 x V
CC
3.2
4.2
µA
µA
mA
mA
V
V
mA
mA
V
V
V
SRAM Operating Supply Current x 32 I x32 SCE = V
IL
, OE = V
IH
, f = 5MHz, V
CC
=
CC
Max, FCE = V
IH
Mode
Standby Current
SRAM Output Low Voltage
SRAM Output High Voltage
Flash Vcc Active Current for Read (1)
Flash Vcc Active Current for Program
or Erase (2)
Flash Output Low Voltage
Flash Output High Voltage
Flash Low Vcc Lock Out Voltage
I
SB
V
OL
V
OH
I
CC1
I
CC2
V
OL
V
OH1
V
LKO
FCE = SCE = V
IH
, OE = V
IH
, f = 5MHz,
V
CC
= Max
I
OL
= 8 mA, V
CC
= Min, FCE = V
IH
I
OH
= -4.0 mA, , V
CC
= Min, FCE = V
IH
FCE = V
IL
, OE = V
IH
, SCE = V
IH
FCE = V
IL
, OE = V
IH
, SCE = V
IH
I
OL
= 12 mA, V
CC
= Min, SCE = V
IH
I
OH
= -2.5 mA, , V
CC
= Min, SCE = V
IH
Notes: 1) The I
CC
current listed includes both the DC operating current and the frequency dependent component (at 5MHz). The
frequency component typically is less than 2mA/MHz, with OE at V
IH
2) I
CC
active while Embedded Algorithim (program or
erase) is in progress 3) DC test conditions: V
IL
= 0.3V, V
IH
= V
CC
- 0.3V
Aeroflex Circuit Technology
2
SCD3851 REV A 5/21/98
Plainview NY (516) 694-6700
SRAM AC Characteristics
(V
CC
= 5.0V, V
SS
= 0V, T
C
= -55°C to +125°C)
Read Cycle
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change
Output Enable to Output Valid
Chip Select to Output in Low Z *
Output Enable to Output in Low Z *
Chip Deselect to Output in High Z *
Output Disable to Output in High Z *
* Parameters guaranteed by design but not tested
Symbol
t
RC
t
AA
t
ACE
t
OH
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
3
0
12
12
0
15
3
0
20
20
–025
Min Max
25
25
25
0
20
–035
Min Max
35
35
35
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
Parameter
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Output Active from End of Write *
Write to Output in High Z *
Data Hold from Write Time
Address Hold Time
* Parameters guaranteed by design but not tested
Symbol
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
OW
t
WHZ
t
DH
t
AH
0
0
–025
Min Max
25
20
20
15
20
0
0
10
0
0
–035
Min Max
35
25
25
20
25
0
0
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SRAM Truth Table
Mode
Standby
Read
Output Disable
Write
SCE
H
L
L
L
OE
X
L
H
X
SWE
X
H
H
L
Data I/O
High Z
Data Out
High Z
Data In
Power
Standby
Active
Active
Active
Aeroflex Circuit Technology
3
SCD3851 REV A 5/21/98
Plainview NY (516) 694-6700
Timing Diagrams — SRAM
Read Cycle Timing Diagrams
Read Cycle 1 (SCE = OE = V
IL
, SWE = V
IH
)
t
RC
A
0-18
t
AA
t
OH
D
I/O
Previous Data Valid
Data Valid
SCE
t
AS
SWE
S
EE
N
OTE
Write Cycle Timing Diagrams
Write Cycle (SWE Controlled, OE = V
IH
)
t
WC
A
0-18
t
AW
t
CW
t
AH
t
WP
t
WHZ
t
DW
Data Valid
t
OW
t
DH
D
I/O
Read Cycle 2 (SWE = V
IH
)
t
RC
A
0-18
t
AA
SCE
t
ACE
t
CLZ
S
EE
N
OTE
Write Cycle (SCE Controlled, OE = V
IH
)
t
WC
A
0-18
t
AW
t
CHZ
S
EE
N
OTE
t
AH
t
CW
t
AS
SCE
OE
t
WP
t
OE
t
OLZ
S
EE
N
OTE
t
OHZ
S
EE
N
OTE
SWE
t
DW
D
I/O
Data Valid
t
DH
D
I/O
High Z
Data Valid
UNDEFINED
DON’T CARE
Note: Guaranteed by design, but not tested.
AC Test Circuit
Current Source
I
OL
AC Test Conditions
Parameter
Typical
0 – 3.0
5
1.5
Units
V
ns
V
To Device Under Test
C
L
= 50 pF
V
Z
~ 1.5 V (Bipolar Supply)
Input Pulse Level
Input Rise and Fall
Input and Output Timing Reference Level
I
OH
Current Source
Notes:
1) V
Z
is programmable from -2V to +7V. 2) I
OL
and I
OH
programmable from 0 to 16 mA. 3) Tester Impedance
Z
O
= 75Ω.
4)
V
Z
is typically the midpoint of V
OH
and V
OL
. 5) I
OL
and I
OH
are adjusted to simulate a typical resistance
load circuit. 6) ATE Tester includes jig capacitance.
4
Aeroflex Circuit Technology
SCD3851 REV A 5/21/98
Plainview NY (516) 694-6700
Flash AC Characteristics – Read Only Operations
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable to Output Valid
Chip Enable to Output High Z (1)
Output Enable High to Output High Z(1)
Output Hold from Address, CE or OE Change, Whichever is First
Note 1. Guaranteed by design, but not tested
Symbol
–60
–70
–90
Units
JEDEC Stand’d Min Max Min Max Min Max
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
t
RC
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
0
60
60
60
30
20
20
0
70
70
70
35
20
20
0
90
90
90
35
20
20
ns
ns
ns
ns
ns
ns
ns
Flash AC Characteristics – Write / Erase / Program Operations, FWE Controlled
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Parameter
Write Cycle Time
Chip Enable Setup Time
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation
Sector Erase Time
Read Recovery Time before Write
Vcc Setup Time
Chip Programming Time
Chip Enable Hold Time
Chip Erase Time
1. Toggle and Data Polling only.
Symbol
JEDEC Stand’d
t
AVAC
t
ELWL
t
WLWH
t
AVWL
t
DVWH
t
WHDX
t
WLAX
t
WHWL
t
WHWH
1
t
WHWH
2
t
WC
t
CE
t
WP
t
AS
t
DS
t
DH
t
AH
t
WPH
–60
–70
–90
Min Max Min Max Min Max
60
0
40
0
40
0
45
20
14
TYP
30
0
0
50
50
50
10
120
120
50
50
10
120
70
0
45
0
45
0
45
20
14
TYP
30
0
50
90
0
45
0
45
0
45
20
14
TYP
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
µs
Sec
µs
µs
Sec
ns
Sec
t
GHWL
t
VCE
t
OEH 1
t
WHWH
3
10
Flash AC Characteristics – Write / Erase / Program Operations, FCE Controlled
(Vcc = 5.0V, Vss = 0V, Tc = -55°C to +125°C)
Parameter
Write Cycle Time
Write Enable Setup Time
Chip Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Enable Pulse Width High
Duration of Byte Programming
Sector Erase Time
Read Recovery Time
Chip Programming Time
Chip Erase Time
Aeroflex Circuit Technology
Symbol
JEDEC Stand’d
t
AVAC
t
WLE
L
t
ELEH
t
AVEL
t
DVEH
t
EHDX
t
ELAX
t
EHEL
t
WHWH
1
t
WHWH
2
t
WC
t
WS
t
CP
t
AS
t
DS
t
DH
t
AH
t
CPH
–60
–70
–90
Min Max Min Max Min Max
60
0
40
0
40
0
45
20
14
TYP
30
0
50
0
50
120
70
0
45
0
45
0
45
20
14
TYP
30
0
50
120
90
0
45
0
45
0
45
20
14
TYP
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
µs
Sec
ns
Sec
Sec
t
GHEL
t
WHWH
3
5
120
SCD3851 REV A 5/21/98
Plainview NY (516) 694-6700
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