BLC6G10-200; BLC6G10LS-200
UHF power LDMOS transistor
Rev. 01 — 19 April 2006
Objective data sheet
1. Product profile
1.1 General description
200 W LDMOS power transistor for base station applications at frequencies from
800 MHz to 1000 MHz.
Table 1:
Typical performance
Typical RF performance at T
case
= 25
°
C in a class-AB production test circuit.
Mode of operation
2-carrier W-CDMA
[1]
f
(MHz)
869 to 894
V
DS
(V)
28
P
L(AV)
(W)
40
G
p
(dB)
20
η
D
(%)
27
ACPR
(dBc)
−39
[1]
Test signal: 3GPP; test model 1; 64 DPCH; PAR = 7.5 dB at 0.01 % probability on CCDF per carrier; carrier
spacing 5 MHz.
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
1.2 Features
I
Typical 2-carrier W-CDMA performance at frequencies of 869 MHz and 894 MHz, a
supply voltage of 28 V and an I
Dq
of 1400 mA:
N
Average output power = 40 W
N
Power gain = 20 dB
N
Efficiency = 27 %
N
ACPR =
−39
dBc
I
Easy power control
I
Integrated ESD protection
I
Excellent ruggedness
I
High efficiency
I
Excellent thermal stability
I
Designed for broadband operation (800 MHz to 1000 MHz)
I
Internally matched for ease of use
1.3 Applications
I
RF power amplifiers for GSM, GSM EDGE, W-CDMA and CDMA base stations and
multi carrier applications in the 800 MHz to 1000 MHz frequency range.
Philips Semiconductors
BLC6G10-200; BLC6G10LS-200
UHF power LDMOS transistor
2. Pinning information
Table 2:
Pin
1
2
3
Pinning
Description
drain
gate
source
[1]
Simplified outline
Symbol
BLC6G10-200 (SOT895-1)
1
3
2
2
3
sym112
1
BLC6G10LS-200 (SOT896-1)
1
2
3
drain
gate
source
[1]
1
3
2
2
1
3
sym112
[1]
Connected to flange
3. Ordering information
Table 3:
Ordering information
Package
Name
BLC6G10-200
-
BLC6G10LS-200 -
Description
plastic flanged cavity package; 2 mounting slots; 2 leads
plastic earless flanged cavity package; 2 leads
Version
SOT895-1
SOT896-1
Type number
4. Limiting values
Table 4:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DS
V
GS
I
D
T
stg
T
j
Parameter
drain-source voltage
gate-source voltage
drain current
storage temperature
junction temperature
Conditions
Min
-
−0.5
-
−65
-
Max
65
+13
<tbd>
+150
200
Unit
V
V
A
°C
°C
BLC6G10-200_6G10LS-200_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Objective data sheet
Rev. 01 — 19 April 2006
2 of 9
Philips Semiconductors
BLC6G10-200; BLC6G10LS-200
UHF power LDMOS transistor
5. Thermal characteristics
Table 5:
Symbol
Thermal characteristics
Parameter
Conditions
Type
Min
Typ
Max
0.52
Unit
K/W
<tbd> <tbd> <tbd> K/W
<tbd> 0.43
T
case
= 80
°C;
BLC6G10-200
R
th(j-case)
thermal resistance
from junction to case P
L
= 40 W
BLC6G10LS-200
6. Characteristics
Table 6:
Characteristics
T
j
= 25
°
C unless otherwise specified
Symbol Parameter
V
(BR)DSS
drain-source breakdown
voltage
V
GS(th)
V
GSq
I
DSS
I
DSX
I
GSS
g
fs
R
DS(on)
C
rs
gate-source threshold voltage
gate-source quiescent voltage
drain leakage current
drain cut-off current
gate leakage current
forward transconductance
drain-source on-state
resistance
feedback capacitance
Conditions
V
GS
= 0 V; I
D
= 0.5 mA
V
DS
= 10 V; I
D
= 150 mA
V
DS
= 28 V; I
D
= 950 mA
V
GS
= 0 V; V
DS
= 28 V
V
GS
= V
GS(th)
+ 3.75 V;
V
DS
= 10 V
V
GS
= 13 V; V
DS
= 0 V
V
DS
= 10 V; I
D
= 7.5 A
V
GS
= V
GS(th)
+ 3.75 V;
I
D
= 5.25 A
V
GS
= 0 V; V
DS
= 28 V;
f = 1 MHz
Min
65
Typ
-
Max
-
Unit
V
<tbd> 2
-
40
-
-
-
-
-
45
-
<tbd> V
5
-
450
µA
A
nA
S
Ω
pF
<tbd> <tbd> <tbd> V
<tbd> -
<tbd> -
<tbd> -
7. Application information
Table 7:
Application information
Mode of operation: 2-carrier W-CDMA; PAR 7.5 dB at 0.01 % probability on CCDF; 3GPP test
model 1; 1-64 PDPCH; f
1
= 871.5 MHz; f
2
= 876.5 MHz; f
3
= 886.5 MHz; f
4
= 891.5 MHz;
RF performance at V
DS
= 28 V; I
Dq
= 1400 mA; T
case
= 25
°
C; unless otherwise specified; in a
class-AB production test circuit
Symbol
P
L(AV)
G
p
IRL
η
D
ACPR
Parameter
average output power
power gain
input return loss
drain efficiency
adjacent channel power ratio
P
L(AV)
= 40 W
P
L(AV)
= 40 W
P
L(AV)
= 40 W
P
L(AV)
= 40 W
Conditions
Min
-
18.5
-
25
-
Typ
40
20
−6.5
27
−39
Max
-
21.5
−4.5
-
−36
Unit
W
dB
dB
%
dBc
7.1 Ruggedness in class-AB operation
The BLC6G10-200 and BLC6G10LS-200 are capable of withstanding a load mismatch
corresponding to VSWR = <tbd> through all phases under the following conditions:
V
DS
= 28 V; I
Dq
= 1400 mA; P
L
= <tbd>; f = 894 MHz.
BLC6G10-200_6G10LS-200_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Objective data sheet
Rev. 01 — 19 April 2006
3 of 9
Philips Semiconductors
BLC6G10-200; BLC6G10LS-200
UHF power LDMOS transistor
8. Package outline
Plastic flanged cavity package; 2 mounting slots; 2 leads
SOT895-1
D
F
A
D
1
U
1
q
B
C
c
1
L
w1
M
A
M
B
M
H
U
2
3
p
E
1
E
A
2
b
w2
M
C
M
Q
0
5
scale
10 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
inches
A
4.1
3.3
b
12.83
12.57
c
0.17
0.14
D
19.9
19.7
D
1
20.42
20.12
E
9.53
9.27
E
1
9.78
9.53
F
1.14
0.89
H
19.94
18.92
L
5.3
4.5
p
3.38
3.12
Q
1.75
1.50
q
27.94
U
1
34.16
33.91
U
2
9.98
9.65
w
1
0.25
0.01
w
2
0.6
0.023
1.345 0.392
0.161 0.505 0.0065 0.785 0.804 0.375 0.385 0.045 0.785 0.209 0.133 0.069
1.100
1.335 0.380
0.130 0.495 0.0055 0.775 0.792 0.365 0.375 0.035 0.745 0.177 0.123 0.059
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
SOT895-1
ISSUE DATE
05-06-28
06-02-21
Fig 1. Package outline SOT895-1
BLC6G10-200_6G10LS-200_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Objective data sheet
Rev. 01 — 19 April 2006
4 of 9
Philips Semiconductors
BLC6G10-200; BLC6G10LS-200
UHF power LDMOS transistor
Plastic earless flanged cavity package; 2 leads
SOT896-1
D
F
A
3
D
1
D
U
1
1
L
c
H
U
2
E
1
E
2
b
w2
M
D
M
Q
0
5
scale
10 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
inches
A
4.1
3.3
b
12.83
12.57
c
0.17
0.14
D
19.9
19.7
D
1
20.42
20.12
E
9.53
9.27
E
1
9.78
9.53
F
1.14
0.89
H
19.94
18.92
L
5.3
4.5
Q
1.75
1.50
U
1
20.70
20.45
U
2
9.98
9.65
w
2
0.6
0.161 0.505 0.0065 0.785 0.804 0.375 0.385 0.045 0.785 0.209 0.069 0.815 0.392
0.023
0.130 0.495 0.0055 0.775 0.792 0.365 0.375 0.035 0.745 0.177 0.059 0.805 0.380
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
OUTLINE
VERSION
SOT896-1
ISSUE DATE
05-06-28
06-02-21
Fig 2. Package outline SOT896-1
BLC6G10-200_6G10LS-200_1
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Objective data sheet
Rev. 01 — 19 April 2006
5 of 9
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