BUS-61555-81L datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> BUS-61555-81L

BUS-61555-81L: DescriptionMicro Peripheral IC; CategoryThe embedded processor and controller Microcontrollers and processors; File Size50KB，4 Pages; ManufacturerData Device Corporation

Download Datasheet Parametric View All

BUS-61555-81L Overview

Micro Peripheral IC

BUS-61555-81L Parametric

Parameter Name	Attribute value
package instruction	,
Reach Compliance Code	unknown
Base Number Matches	1

Preview

Download Datasheet

View All

BUS-61553

MIL-STD-1553 ADVANCED INTEGRATED

MUX (AIM ) HYBRID

ALSO

SEE

IDE

R’S GU

USE

DESCRIPTION

DDC’s

BUS-61553

Advanced

Integrated Mux (AIM) Hybrid is a

complete

MIL-STD-1553

Bus

Controller (BC), Remote Terminal

Unit (RTU), and Bus Monitor (MT)

device. Packaged in a single 78-pin

DIP package, the BUS-61553 con-

tains dual low-power transceivers,

complete BC/RT/MT protocol logic, a

MIL-STD-1553-to-host interface unit

and 8K x 16 RAM.

Using an industry standard dual

transceiver and standard status and

control signals, the BUS-61553 sim-

plifies system integration at both the

MIL-STD-1553 and host processor

interface levels.

All 1553 operations are controlled

through the CPU access to the

shared 8K x 16 RAM. To ensure

maximum design flexibility, memory

control lines are provided for attach-

ing external RAM to the BUS-61553

address and data buses and for dis-

abling internal memory; the total

combined memory space can be

expanded to 64K x 16. All 1553 trans-

fers are entirely memory-mapped;

thus the CPU interface requires

minimal hardware and/or software

support.

The BUS-61553 operates over the

full military -55°C to +125°C temper-

ature range. Available screened to

MIL-PRF-38534, the BUS-61553 is

ideal for demanding military and

industrial microprocessor-to-1553

interface applications.

FEATURES

• Fully Intergrated Terminal

Including:

–Dual Transceiver

–BC/RT/MT Protocol

–Memory Management Unit

–Processor lnterface Logic

–8K x 16 RAM

• CMOS and Bipolar Technologies

• Internal Interrupt Status and Time

Tag Registers

• High Reliability

• 883B Processing Available

BUS-25679

DATA

BUS A

TRANSCEIVER A

TX INH

CONTENTION

RESOLVER

INTERRUPT

GENERATOR

CLOCK IN

CHANNEL A

ENCODER/

DECODER

MEMORY

TIMING

CPU

TIMING

MSTRCLR

SELECT

STRBD

READYD

RD/WR

MEM/REG

EXTEN

EXTLD

INT

TRANSFORMER A

768

µs

TIME OUT

PROTOCOL

CONTROLLER

A15-A00

BUS-25679

DATA

BUS B

TX INH

TRANSCEIVER B

D15-D00

TRANSFORMER B

CHANNEL B

ENCODER/

DECODER

8K x 16

SHARED RAM

PARITY

CHECKER

RT ADDR

RTAD0

RTAD1

RTAD2

RTAD3

RTAD4

RTAD P

RTPARERR

RAM

FIGURE 1. BU-61553 BLOCK DIAGRAM

Recommended Resources

Independently adjustable timer circuit for on and off times

Automatic charging and discharging circuit diagram using thyristor

Micro AM/FM Stereo Radio

High performance noise reduction circuit

555 zero volt switching circuit

555 multi-function home appliance socket circuit (2)

Some Problems in PROTEL Operation: When drawing a schematic, I found that the network label number is NetLabel240. I want to restore it to NetLabel0 or NetLabel1. I would like to ask how to set it in Protel? Thank you!...; ben007 Analog electronics

I was full of confidence after I finished drawing the board, but when I got the board, I realized that there were many places I had not paid attention to!: The vias have been reduced in size, and now the screws can't be installed! :lol[b][color=#5E7384]This content was created by EEWORLD forum user [size=3]蓝雨夜[/size]. If you want to reprint or use it for...; 蓝雨夜 Talking

Problems encountered by novices when trying to make PCBs: I just learned AD10 a few days ago, and my friend sent me a schematic diagram and PCB diagram for me to practice. I encountered many problems: 1. I have already made the schematic library, but when ma...; 成车趁 PCB Design

Communication Post-State-Oriented Embedded Development Framework: First of all, I would like to state that the following are just my personal ideas. The specific feasibility and implementation still need to go through a lot of torture. When developing a single-chip ...; LQ77630 Embedded System

Anyone who has used CCS to compile MSP430G2, please come in, it's urgent! ! ! !: How to use CCS5.1 to view PWM waveform, the output IO ports are p2.2 and P2.3 respectively, please explain the specific operation:Sad: :Sad: :Sad: :Sad:...; starry22 Microcontroller MCU

MSP430F5438 study notes basic io: [p=26, null, left][color=#000][font=Arial]1. Familiar with the clock system of MSP430[/font][/color][/p][p=26, null, left][color=#000][font=Arial]2. Operate GPIO[/font][/color][/p][code]// Clock defau...; qinkaiabc Microcontroller MCU

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components