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BS62LV2565SCP70

Description
Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, SOP-28
Categorystorage    storage   
File Size376KB,10 Pages
ManufacturerBrilliance
Environmental Compliance
Download Datasheet Parametric View All

BS62LV2565SCP70 Overview

Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, SOP-28

BS62LV2565SCP70 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
package instructionSOP, SOP28,.45
Reach Compliance Codeunknown
Maximum access time70 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G28
length18.11 mm
memory density262144 bit
Memory IC TypeSTANDARD SRAM
memory width8
Humidity sensitivity level3
Number of functions1
Number of terminals28
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP28,.45
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Maximum seat height2.844 mm
Maximum standby current4e-7 A
Minimum standby current1.5 V
Maximum slew rate0.035 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
width8.407 mm
Base Number Matches1
BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
32K X 8 bit
DESCRIPTION
BS62LV2565
• Wide Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.4uA (Typ.) CMOS standby current
• High speed access time :
-55
55ns (Max.) = 5.0V
-70
70ns (Max.) = 5.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
The BS62LV2565 is a high performance, very low power CMOS
Static Random Access Memory organized as 32,768 words by 8 bits
and operates from a wide range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.4uA and maximum access time of 55ns in 5V operation.
Easy memory expansion is provided by an active LOW chip enable(CE)
, and active LOW output enable(OE) and three-state output drivers.
The BS62LV2565 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2565 is available in the JEDEC standard 28 pin 330mil
Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP and 8mmx13.4mm
TSOP (normal type).
PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV2565SC
BS62LV2565TC
BS62LV2565PC
BS62LV2565JC
BS62LV2565DC
BS62LV2565SI
BS62LV2565TI
BS62LV2565PI
BS62LV2565JI
BS62LV2565DI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
(ns)
Vcc=5.0V
(I
CCSB1
, Max)
Vcc=5.0V
POWER DISSIPATION
STANDBY
Operating
(I
CC
, Max)
Vcc=5.0V
PKG
TYPE
SOP-28
TSOP-28
PDIP-28
SOJ-28
DICE
SOP-28
TSOP-28
PDIP-28
SOJ-28
DICE
0 C to +70 C
O
O
4.5V ~ 5.5V
55 / 70
1.0uA
35mA
-40 C to +85 C
O
O
4.5V ~ 5.5V
55 / 70
2.0uA
40mA
PIN CONFIGURATIONS
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
BS62LV2565SC
BS62LV2565SI
BS62LV2565PC
BS62LV2565PI
BS62LV2565JC
BS62LV2565JI
BLOCK DIAGRAM
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
A5
A6
A7
A12
A14
A13
A8
A9
A11
Buffer
Address
Input
18
Row
Decoder
512
Memory Array
512 x 512
512
Column I/O
Write Driver
Sense Amp
64
Column Decoder
12
CE
WE
OE
Vdd
Gnd
A4 A3 A2 A1 A0 A10
Control
Address Input Buffer
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
BS62LV2565TC
BS62LV2565TI
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
8
Data
Output
Buffer
8
Brilliance Semiconductor, Inc
.
reserves the right to modify document contents without notice.
R0201-BS62LV2565
1
Revision 2.3
Jan.
2004
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