The B9846 is a high performance, low-skew, low jitter buffer
designed to distribute differential clocks in high-speed applica-
tions. The B9846 generates six differential pair clock outputs
to support two DDR Dimms. In addition, the B9846 features a
feedback clock output, FBOUT. This output is for the chipset
or other B9846 devices and/or one of Cypress’s zero-delay
buffers. Typically, The B9846 is used with C9846 clock synthe-
sizer for the VIA Pro 266 chipset, and with the C9854 clock
synthesizer for the VIA KT266 chipset.
The I
2
C interface enables/disables differential pair outputs.
This feature allows flexibility in system power management.
Block Diagram
FBOUT
BUFIN
DDRT0
DDRC0
DDRT1
DDRC1
SCLK
SDATA
Pin Configuration
FBOUT
VSS
DDRT0
DDRC0
VDD2.5V
VSS
DDRT1
DDRC1
VDD2.5V
BUFIN
VSS
DDRT2
DDRC2
VDD2.5V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
DDRT5
DDRC5
VDD2.5V
VSS
DDRT4
DDRC4
VDD2.5V
VSS
DDRT3
DDRC3
VDD2.5V
SCLK
SDATA
Control
Logic
DDRT2
DDRC2
DDRT3
DDRC3
DDRT4
DDRC4
DDRT5
DDRC5
Cypress Semiconductor Corporation
Document #: 38-07299 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 22, 2002
B9846
Pin Description
Pin No.
10
3,7,12,19,23,27
4,8,13,18,22,26
1
Pin Name
BUFIN
DDR(0:5)T
DDR(0:5)C
FBOUT
PWR
VDD2.5V
VDD2.5V
VDD2.5V
VDD2.5V
I/O
I
O
O
O
Description
Clock Input.
2.5V for DDR-ONLY.
True DDR Clock Outputs.
Buffered copy of the signal
applied at BUFIN.
Complementary DDR Clock Outputs.
Inverted copy of
the signal applied at BUFIN.
Feedback Clock Output.
Single ended buffered copy of
the signal applied at BUFIN. This clock is in phase with
the True DDR clock outputs. It is generally used to drive
the DCLKI of chipset memory controller.
Serial Clock Input.
Clocks data at SDATA into the internal
register.
Serial Data Input.
Input data is clocked to the internal
register to enable/disable individual outputs. This
provides flexibility in power management.
2.5V power supply
Common ground
16
15
SCLK
SDATA
I, PU
[1]
I/O, PU
5,9,14,17,21,25
2,6,11,20,24,28
VDD2.5
VSS
VDDD
2.5V
4"
DDRT (0:5)
60 Ohm
4"
R
T
= 120 Ohm
16PF
PROBE
DDRC (0:5)
60 Ohm
16PF
33
4"
60 Ohm
10PF
PROBE
FBOUT
PROBE
Figure 1. Differential Signal Using Direct Termination Resistor
A bypass capacitor (0.1
µF)
should be placed as close as
possible to each positive power pin (< 0.2”). If these bypass
capacitors are not close to the pins their high-frequency
filtering characteristic will be cancelled by the lead inductance
of the traces.
Note:
1. PU = Internal pull-up, typical value of 640K
Ω
.
Document #: 38-07299 Rev. *A
Page 2 of 7
B9846
Serial Control Registers
Following the acknowledge of the Address byte, two additional
bytes must be sent:
1. Command code
2. Byte count.
Byte(0:5) are dummy bytes and are reserved. These bytes will
be ignored and acknowledged. For more details on the use of
the I
2
C interface, see our application note entitled
2-Wire I2C
Control Interface
(AN0022).
Byte 6: Output Register
(1 = Enable, 0 = Disable)
Bit
7
6
5
4
3
2
1
0
@Pup
0
0
0
1
1
1
1
1
Pin No.
–
–
–
1
–
26,27
22,23
18,19
Description
Reserved
Reserved
Reserved
FBOUT
Reserved
DDRT/C5
DDRT/C4
DDRT/C3
Byte 7: Output Register
(1 = Enable, 0 = Disable)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin No.
–
–
–
12,13
–
7, 8
–
3, 4
Description
Reserved
Reserved
Reserved
DDRT/C2
Reserved8
DDRT/C1
Reserved
DDRT/C0
Document #: 38-07299 Rev. *A
Page 3 of 7
B9846
Maximum Ratings
[2]
Input Voltage Relative to V
SS
............................... V
SS
– 0.3V
Input Voltage Relative to V
DD
.............................. V
DD
+ 0.3V
Storage Temperature .................................. –65°C to +150°C
Operating Temperature ..................................... 0°C to +70°C
Maximum Power Supply .................................................5.5V
This device contains circuitry to protect the inputs against
damage due to high-static voltages or electric fields; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
IN
and V
OUT
should be constrained to
the range:
V
SS
< (V
IN
or V
OUT
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
VDD2.5V = 2.5V + 5%, T
A
= 0°C to +70°C
[3]
Parameter
V
IL
V
IH
V
IL1
V
IH1
I
IH
I
IL
I
OL
I
OH
V
OL
V
OH
V
OUT
V
OX
I
OZ
I
DD
I
DDS
C
IN
Description
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input High Current
Input Low Current
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Voltage Swing
[6]
Output Crossing Voltage
[7]
High-Impedance Output
Current
V
O
= GND or V
O
= V
DD
V
DD
= 2.375V, V
OUT
= 1.2V
V
DD
= 2.375V, V
OUT
= 1V
V
DD
= 2.375V, I
OL
= 12 mA
V
DD
= 2.375V, I
OH
= –12 mA
1.7
0.7
(V
DD
/2) – 0.2
–10
–
TBD
–
–
5
V
DD
/2
V
DD
+0.6
(V
DD
/2) + 0.2
10
TBD
TBD
–
26
–18
35
–32
0.6
V
IN
= V
DD
, BUFIN, PD#
BUFIN
2.0
10
–TBD
µA
µA
mA
mA
V
V
V
V
µA
mA
mA
pF
Test Conditions
SDATA , SCLK
2.2
Min.
Typ.
–
–
1.0
Max.
1.0
Units
V
V
Dynamic Supply Current
[8]
All V
DD
, FO = 133 MHz
Shutdown Supply Current All V
DD
Input Pin Capacitance
Notes:
2.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Unused inputs must be held high or low to prevent them from floating.
4. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the
complementary input level. See
Figure 1.
AUTHOR: NO CORRESPONDING FOOTNOTE IN THE TEXT.
5. Differential cross-point input voltage is expected to track V
DD
and is the voltage at which the differential signals must be crossing.
AUTHOR: NO CORRE-
SPONDING FOOTNOTE IN THE TEXT.
6. For load conditions, see
Figure 1.
7. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120
Ω
resistor. See
Figure 1.
8. All outputs switching loaded with 16 pF in 60
Ω
environment. See
Figure 1.
Document #: 38-07299 Rev. *A
Page 4 of 7
B9846
AC Parameters
VDD2.5V = 2.5V + 5%, T
A
= 0°C to +70°C
[2]
Parameter
fCLK
tDC
Tr / Tf
tDC
Description
Operating Clock Frequency
Input Clock Duty Cycle
DDR Output Clocks Rise/Fall Edge Rate
Output Duty Cycle
[4]
Single ended output
Half-period jitter
Low-to-High Propagation Delay, BUFIN to
Output
High-to-Low Propagation Delay, BUFIN to
Output
Any-Output-to-Any-Output Skew
Note 9
20% to 80%
Measured at 1.4V for 3.3V
outputs. Measured at V
DD
/2 for
2.5V outputs
Note 9
Test Conditions
Min.
60
48
1.0
INDC –
2%
–100
1.5
1.5
3.5
3.5
–
Typ.
Max.
170
52
3.0
INDC +
2%
100
6
6
150
Units
MHz
%
V/ns
%
tHCS
tPLH
tPHL
tSKEW
ps
ns
ns
ps
Notes:
9. Measured at crossing point (VOC). DDRT/C to FBOUT skew is measured at 50% (for FBOUT) and at crossing point (VOC) for DDRT/C.
10. Parameters are guaranteed by design and characterization. Not 100% tested in production.
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