PRELIMINARY
B9680
Product Features
§
§
§
§
§
§
§
18 output buffer for high clock fanout applications
Each output can be disabled Through SMBUS
3.3Volts typical operation supply
Frequency range 10 Mhz to 166.6 Mhz
< 250ps skew between output clocks
48-pin SSOP package
Tri-state enable for system testing.
SMBUS System Clock Buffer
Product Description
The Cypress B9680 is a high fanout system clock
buffer. Its primary application is to create the large
quantity of clocks needed to support a wide range of
applications that requires those clock loads signal that
are referenced to a single existing clock. Loads of up to
30 pF are supported. The main application of this
component is to redistribute SDRAM clocks from their
generating devices typically the 440BX chipset to their
loads, the SDRAM modules. The creation of EMI and
the degradation of waveform rise and fall times is
greatly reduced by running a single reference clock
trace to this device and then using it to regenerate the
clock that drives shorter traces. Using these devices
EMI is therefore minimized and board layout is
simplified.
Block Diagram
Pin Configuration
NC
VDD
CLK[1:2]
VDD
CLK[3:4]
REFIN
VDD
CLK[5:6]
VDD
CLK[7:8]
VDD
CLK[9:10]
VDDC
OE
SDATA
SCLK
VDD
CLK[11:12]
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
VDD
CLK18
CLK17
VSS
VDD
CLK16
CLK15
VSS
OE
VDD
CLK14
CLK13
VSS
VDD
CLK12
CLK11
VSS
VDD
CLK10
VSS
VSSC
SCLOCK
NC
VDD
CLK1
CLK2
VSS
VDD
CLK3
CLK4
VSS
REFIN
VDD
CLK5
CLK[13:14]
Control
Logic
CLK6
VSS
VDD
CLK7
CLK8
VSS
VDD
CLK9
VSS
VDDC
SDATA
VDD
CLK[15:16]
VDD
CLK[17,18]
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07074 Rev. **
9/15/2000
Page 1 of 10
PRELIMINARY
B9680
SMBUS System Clock Buffer
Pin Description
PIN
No.
11
4,5,8,9,1
3,14,17,1
8,,21,28,
31,32,35,
36,40,41,
44,45
38
Pin
Name
REFIN
CLK(1:18)
PWR
VDD
VDD
I/O
I
O
TYPE
PAD
BUF1
Description
This pin is connected to the input reference clock. This clock
must be in the range of 10.0 to 166.6 Mhz.
Low skew output clock
OE
-
I
PAD
24
25
6, 10, 15,
19, 22,
27, 30,
34, 39,
43
3, 7, 12,
16, 20,
29, 33,
37, 42,
46
23
26
1,2,47,48
SDATA
SDCLK
VSS
VDDC
VDDC
I
I
PWR
PAD
PAD
-
Buffer Output Enable pin. When forced to a logic low level this
pin is used to place all output clocks (CLK1:18} in a tri state
condition. This feature facilitates in production board level
testing to be easily implemented for the clocks that this device
produces. Has internal pull-up resistor, typically 250KΩ
Serial data of SMBUS 2-wire control interface. Has internal pull-
up resistor, typically 250KΩ
Serial clock of SMBUS 2-wire control interface. Has internal
pull-up resistor, typically 250KΩ
Ground pins for clock output buffers. These pins must be
returned to the same potential to reduce output clock skew.
VDD
-
PWR
-
Power for output clock buffers.
VDDC
VSSC
NC
-
-
PWR
PWR
-
-
Power for core logic.
Ground supply pins for internal core logic.
No connection.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07074 Rev. **
9/15/2000
Page 2 of 10
PRELIMINARY
B9680
SMBUS System Clock Buffer
2-Wire SMBUS Control Interface
The 2-wire control interface implements a write only slave interface. The device cannot be read back. Sub-addressing is
not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control
interface allows each clock output to be individually enabled or disabled.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK
is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer
cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.
The device will respond to writes to 10 bytes (max) of data to address
D2
by generating the acknowledge (low) signal on
the SDATA wire following reception of each byte. The device will not respond to any other control interface conditions.
Previously set control registers are retained.
Serial Control Registers
NOTE:
The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated.
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “Command
Code
“ byte, and
2) “Byte
Count”
byte.
Although the data (bits) in these two bytes are considered “don’t care”, they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte
0, Byte 1, Byte 2, ....) will be valid and acknowledged.
Byte 0: Clock
Output Select Register
(1
= enable, 0 = Stopped, Default=FF)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
18
17
14
13
9
8
5
4
Description
CLK8 (Active = 1, Forced low = 0)
CLK7 (Active = 1, Forced low = 0)
CLK6 (Active = 1, Forced low = 0)
CLK5 (Active = 1, Forced low = 0)
CLK4 (Active = 1, Forced low = 0)
CLK3 (Active = 1, Forced low = 0)
CLK2 (Active = 1, Forced low = 0)
CLK1 (Active = 1, Forced low = 0)
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07074 Rev. **
9/15/2000
Page 3 of 10
PRELIMINARY
B9680
SMBUS System Clock Buffer
Serial Control Registers (Cont.)
Byte 1:
Clock Output Register
(1 = enable, 0 = Stopped, Default=FF)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
1
1
1
1
1
1
Pin#
45
44
41
40
36
35
32
31
Description
CLK18 (Active = 1, Forced low = 0)
CLK17(Active = 1, Forced low = 0)
CLK16 (Active = 1, Forced low = 0)
CLK15 (Active = 1, Forced low = 0)
CLK14 (Active = 1, Forced low = 0)
CLK13(Active = 1, Forced low = 0)
CLK12 (Active = 1, Forced low = 0)
CLK11 (Active = 1, Forced low = 0)
Byte 2:
Clock Output Register
(1 = enable, 0 = Stopped, Default=C0)
Bit
7
6
5
4
3
2
1
0
@Pup
1
1
0
0
0
0
0
0
Pin#
28
21
-
-
-
-
-
-
Description
CLK10 (Active = 1, Forced low = 0)
CLK9 (Active = 1, Forced low = 0)
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Maximum Ratings
This device contains circuitry to protect the inputs
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD:VDD + 0.3V
Storage Temperature:
Operating Temperature:
Maximum ESD protection
Maximum Power Supply:
-65ºC to + 150ºC
0ºC to +85ºC
2KV
5.5V
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07074 Rev. **
9/15/2000
Page 4 of 10
PRELIMINARY
B9680
SMBUS System Clock Buffer
DC Parameters
Characteristic
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Current (@VIL =
VSS)
Input High Current (@VIL =
VDD)
Tri-State leakage Current
Dynamic Supply Current
Dynamic Supply Current
Static Supply Current
Input pin capacitance
Output pin capacitance
Pin Inductance
Symbol
VIL1
VIH1
VIL2
VIH2
IIL
IIH
Ioz
Idd133
Idd100
Isdd
Cin
Cout
Lpin
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Min
-
2.0
-
2.2
-66
Typ
-
-
-
-
Max
1.0
-
1.0
-
-5
5
10
160
90
400
5
6
7
Units
Vdc
Vdc
Vdc
Vdc
µA
µA
µA
mA
mA
µA
pF
pF
nH
Input clock=133MHz, all outputs ON and
w/30pF
Input clock=100MHz, all outputs ON and
w/30pF
All outputs disabled, no input clock
Applicable to I²C’s SDATA and SCLK
inputs
For internal Pull up resistors, Note 1
Conditions
Applicable to OE input
VDD = VDDC = 3.3V
±5%,
TA = 0ºC to +70ºC
Note 1:
Applicable to SDATA, and SCLK inputs. The pull-up resistor has a typical value of 250KΩ, but may vary between 200KΩ to 500KΩ
AC Parameters
Characteristic
Output Duty Cycle
Buffer out/out Skew All
Buffer Outputs
Buffer input to output Delay
Jitter Cycle to Cycle*
Jitter Absolute (Peak to
Peak)*
Symbol
-
t
SKEW
t
DLY
T
JCC
T
Jabs
Min
45
-
1.0
Typ
50
-
-
Max
55
250
5.0
100
150
Units
%
pS
nS
pS
pS
@ 30 pF loading, 133MHz clock
@ 30 pF loading, 133.3MHz clock
Conditions
Measured at 1.5V (50/50 in)
30 pF Load Measured at 1.5V
VDD=VDDC = 3.3V
±5%,
TA = 0ºC to +70ºC
*This jitter is additive to the input clock’s jitter.
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07074 Rev. **
9/15/2000
Page 5 of 10
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