622 Mbps Single Mode Fiber
Transceiver for ATM, SONET
OC-12/SDH STM-4
Technical Data
CDX2622
Features
• 1300 nm Single Mode
Transceiver for Links up to
15 Km
• Compliant with ATM Forum
622.08 Mb/s Physical Layer
Specification AF-PHY-
0046.000
• Compliant with
Specifications Proposed to
ANSI T1E1.2 Committee for
Inclusion in T1.646-1995
Broadband ISDN and
T1E1.2/96-002 SONET
Network to Customer
Installation Interface
Standards
• Compliant with ANSI
T1.105.06 SONET Physical
Layer Specifications
Standard
• Multisourced 2 x 9 Pin-out
Package Style
Interchangeable with
Multimode HFBR-5207
• Integral Duplex SC
Connector Receptacle
Compliant with TIA/EIA and
IEC Standards
• Single +5 V Power Supply
Operation and PECL Logic
Interfaces
• Incorporates Hewlett-
Packard’s Eyesafe Laser
Subassembly
• Integral Digital PLL
Provides Regenerated
Differential Clock Output
• Integral Decision Circuit
Provides Retimed
Differential Data Output
• Laser Bias Monitor, Refer-
ence Clock, Transmitter
Disable and Laser Power
Monitor Functions
• Two Temperature Ranges:
0
°
C to +70
°
C –CDX2622B/D
-40
°
C to +85
°
C
–CDX2622A/C
• Wave Solder and Aqueous
Wash Process Compatible
• Manufactured in an ISO
9001 Certified Facility
Applications
• ATM 622 Mb/s Links
• SONET OC-12/SDH STM-4
Interconnections
Description
General
The CDX2622 is a 1300 nm laser-
based duplex SC receptacle 2 x 9
transceiver with integral clock
and data recovery circuits. It
provides a cost-effective solution
to medium haul 622 Mb/s data
link requirements.
This compact transceiver requires
a single +5 V source and
contains the following data, clock
and monitoring features as
depicted in Figure 1: differential
data input, differential retimed
data output, recovered clock
output, signal detect, laser bias
monitor, transmitter disable and
an option to generate a local
timing signal from an external,
low-frequency reference clock.
The external timing signal acts as
the reference clock when
incoming optical signals become
undetectable.
Multimode Transceiver
The CDX2622 is designed as a
drop in replacement for the
HFBR-5207, a multimode, duplex
SC transceiver capable of a
500 m transmission distance.
This multimode product uses the
same pin-out enabling a single
board design for both multimode
and singlemode links.
5965-5858E (2/97)
351
Transmitter Section
The transmitter section of the
CDX2622 is similar to 1300 nm
single mode transceivers in use at
the 155 Mb/s rate. It consists of a
1300 nm InGaAsP laser in an eye-
safe optical subassembly (OSA)
which mates to the fiber cable.
The laser OSA is driven by a
custom, silicon bipolar IC which
converts differential input PECL
logic signal into an analog laser
drive current.
Receiver Section
The receiver section of the
transceiver provides a full set of
features including an integral
clock and data recovery (CDR)
circuit together with an optional,
selectable receiver local clock
source.
The receiver utilizes an InGaAs
PIN photodiode mounted
together with a GaAs transimped-
ance preamplifier IC in an OSA.
This OSA is connected to a
custom, silicon bipolar circuit
providing post-amplification and
quantization, CDR function, and
optical signal detection.
BAUD INTERVAL
ELECTRICAL SUBASSEMBLY
RETIMED DATA 2
RECOVERED CLOCK 2
REFERENCE CLOCK
LOCK-TO-REFERENCE
SIGNAL DETECT
DATA 2
LASER BIAS MONITOR
LASER
DRIVER
IC
CLOCK & DATA
RECOVERY
AND POST
AMPLIFIER IC
PRE-
AMP IC
PIN PHOTODIODE
OPTICAL
SUB-
ASSEMBLIES
DUPLEX SC
RECEPTACLE
LASER
TOP VIEW
POWER
MONITOR
TRANSMIT
DISABLE
Figure 1. Block Diagram.
CDR Function
In normal operation, the CDR
data loop is able to acquire and
maintain bit lock without the use
of the optional, external refer-
ence clock. This loop consists of
a patented phase/frequency
detector with false-lock protec-
tion. The recovered clock is used
to re-time the quantizer data
output, which completes the full
CDR function.
The relative timing relationship
between the output re-timed data
and the recovered clock signals is
shown graphically in Figure 2.
For input optical power greater
than the specified receiver
sensitivity of -28 dBm, the bit-
error-ratio will be better than
1 x 10
-10
. As the input power is
decreased by several dB, the bit-
error-ratio degrades. Within 1 dB
below the 1 x 10
-2
BER input
optical power level, the CDR will
begin to lose lock and the clock
frequency will drift from
622.08 MHz. Once the CDR loses
lock, the clock frequency will
sweep through the entire V
CO
range, about 540 to 700 MHz.
The rate of the sweep is inversely
proportional to the input optical
power and will reach its
maximum at a point of 2 dB
below the lock point. Since data
is retimed to the clock, a loss of
lock will produce an output data
stream consisting of randomly
switching data bits, i.e. noise.
V
OH
RD
V
OL
V
OH
RD
V
OL
V
OH
CLK
V
OL
V
OH
CLK
V
OL
CLOCK PERIOD
Figure 2. Relative Timing Relationship Between Output Retimed Data and
Recovered Clock Signals.
352
Receiver Signal Detect
As the input optical power is
decreased, Signal Detect will
switch from high to low (de-
assert point) at a point between
3 dB below minimum guaranteed
sensitivity and the no light input
level. As the input optical power
is increased from very low levels,
Signal Detect will switch back
from low to high (assert point).
The assert level will be at least
0.5 dB higher than the de-assert
level. This single- ended low-
power PECL output is designed
to drive a standard PECL input
using a 10 kΩ load instead of the
normal 50
Ω
PECL load.
Reference Clock
In applications where the receiver
recovered clock frequency is not
allowed to drift upon loss of input
optical signal, the CDX2622 has
the ability to generate a local
clock output by multiplying an
optional, external 19.44 MHz
reference clock up to the OC-12/
STM4 (622.08 MHz) rate. This
feature is possible because the
clock recovery system consists of
two loops: a data loop which
locks onto the incoming optical
data stream, and a second
reference loop which locks onto
the optional external reference
clock.
This optional feature is initiated
by applying a Lock-to-Reference
logic signal to pin 2 (Lck Ref-)
which switches the loop to the
external reference clock and
disables the received data
outputs. Pin 2 (Lck Ref-) can be
driven from the Signal Detect pin
15 (SD) output or from other
logic further upstream in the
ATM interface which may be
monitoring the quality of the
received data stream.
Transceiver Specified for
Wide Temperature Range
Operation
The CDX2622 is specified for
operation over normal
commercial temperature range of
0° to +70°C (CDX2622B/D) or
the extended temperature range
of -40° to +85°C (CDX2622A/C).
Other Members of HP
622 Mb/s Product Family
• HFBR-5207 1300 nm LED-
based transceiver in 2 x 9
package for 500 m links with
MMF cables (drop in replace-
ment for CDX2622)
• SDX1622 1300 nm laser based
1 x 9 SC receptacle transceiver
for 15 km links with SMF
cables (without CDR)
• HFBR-5208 1300 nm LED-
based 1 x 9 SC receptacle
transceiver for 500 m links with
MMF cables (drop in
replacement for SDX1622)
• XMT5360-622 1300 nm laser-
based transmitter in pigtailed
package for 2 km and 15 km
links with SMF cables
• XMT5160-622 1300 nm laser-
based transmitter in pigtailed
package for 40 km links with
SMF cables
• RCV1201D-622 receiver in
pigtailed package for 2 km, 15
km and 40 km links with SMF
cables
• RGR1622 receiver with integral
clock and data recovery in
pigtailed packages for 2 km,
15 km and 40 km.
tions other than the required BER
= 1 x 10
-10
of the ATM Forum
622.08 Mbps Physical Layer
Standard. The typical tradeoff of
BER versus Relative Input Optical
Power is shown in Figure 3. The
Relative Input Optical Power in
dB is referenced to the Input
Optical Power parameter value in
the Receiver Optical Characteris-
tics table. For better BER
condition than 1 x 10
-10
, more
input signal is needed (+dB).
Recommended Circuit
Schematic
In order to insure proper
functionality of the CDX2622 a
recommended circuit is provided
in Figure 4. When designing the
circuit interface, there are a few
fundamental guidelines to follow.
For example, in the Recom-
mended Circuit Schematic figure
the differential data lines should
be treated as 50
Ω
Microstrip or
stripline transmission lines. This
will help to minimize the parasitic
inductance and capacitance
effects. Proper termination of the
differential data and clock signals
will prevent reflections and
ringing which would compromise
the signal fidelity and generate
10
-2
10
-3
LINEAR EXTRAPOLATION
OF 10
-4
THROUGH 10
-7
DATA POINTS
ACTUAL DATA
POINTS
BIT ERROR RATIO
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
10
-12
10
-13
10
-14
10
-15
Applications Information
Typical BER Performance of
Receiver versus Input Optical
Power Level
The CDX2622 transceiver can be
operated at Bit-Error-Rate condi-
-5
-4
-3
-2
-1
0
1
2
3
RELATIVE INPUT OPTICAL POWER – dBm AVG.
Figure 3. Relative Input Optical
Power dBm Average.
353
unwanted electrical noise. Locate
termination at the received signal
end of the transmission line. The
length of these lines should be
kept short and of equal length to
prevent pulse-width distortion
and data-to-clock timing skew
from occurring. For the high
speed signal lines, differential
signals should be used, not
single-ended signals, and these
differential signals need to be
loaded symmetrically to prevent
unbalanced currents from flowing
which will cause distortion in the
signal.
Maintain a solid, low inductance
ground plane for returning signal
currents to the power supply.
Multi-layer plane printed circuit
board is best for distribution of
V
CC
, returning ground currents,
forming transmission lines and
shielding. Also, it is important to
suppress noise from influencing
the fiber-optic transceiver per-
formance, especially the receiver
and the clock recovery circuits.
Proper power supply filtering of
V
CC
for this transceiver is
accomplished by using the
recommended, separate filter
circuits shown in Figure 4. These
filter circuits suppress V
CC
noise
of 50 mV peak-to-peak or less
over a broad frequency range.
This prevents receiver sensitivity
degradation as well as false-lock
or loss-of-lock in the clock
recovery circuitry due to V
CC
noise. It is recommended that
surface-mount components be
used. Use tantalum capacitors for
the 10
µF
capacitors and mono-
lithic, ceramic bypass capacitors
for the 0.1
µF
capacitors. Also, it
is recommended that a surface-
mount coil inductor of 1
µH
be
used. Ferrite beads can be used
to replace the coil inductors when
using quieter V
CC
supplies, but a
coil inductor is recommended
354
over a ferrite bead. Coils with a
low, series dc resistance
(<0.7
Ω)
and high, self-
resonating frequency are recom-
mended. All power supply
components need to be placed
physically next to the V
CC
pins of
the receiver and transmitter. Use
a good, uniform ground plane
with a minimum number of holes
to provide a low-inductance
ground current return for the
power supply currents.
In addition to these recommenda-
tions, Hewlett- Packard’s Applica-
tion Engineering staff is available
for consulting on best layout
practices with various vendors
mux/demux, clock generator, and
Rx
NO INTERNAL
CONNECTION
Tx
NO INTERNAL
CONNECTION
TERMINATE
AT CLOCK
INPUTS
V
CC
R11
REF
CLK
R9
R14
,,,,,
CDX2622
TOP VIEW
Rx
V
EE
18
RD
17
RD
16
SD
15
Rx
V
CC
14
Tx
V
CC
13
TD
12
TD
11
C7
R13
LCK
REF CLK REF CLK
1
2
3
CLK
4
L
MON
L
MON
(-)
(+) Tx
DIS
5*
6*
7*
NC
8*
OPTIONAL
C8
C1
C2
L1
L2
R2
V
CC
TERMINATE
AT THE
DEVICE
INPUTS
V
CC
R5
R7
C3
C4
R1
C6
R6
R8
LOCATE
FILTER
AT VCC
PINS
R15
Tx
V
EE
10
P
MON
9*
CLK
CLK
R10
R12
VCC
RD
RD
SD
TD
TD
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR PECL SIGNALS NEED TO BE LOCATED AT THE INPUT OF DEVICES
RECEIVING THOSE PECL SIGNALS.
R1 = R4 = R6 = R8 = R10 = R12 = R14 = 130
Ω.
R2 = R3 = R5 = R7 = R9 = R11 = R13 = 82
Ω.
C1 = C2 = C3 = C5 = C6 = C7 = 0.1 µF.
C4 = C8 = 10 µF.
L1 = L2 = 1 µH COIL.
R15 = 10 kΩ.
FOR THE SINGLE MODE CDX2622 TRANSCEIVER, PINS 5–9 ARE USED FOR LASER DIODE BIAS
AND OPTICAL POWER MONITORING AS WELL AS TO PROVIDE A TRANSMITTER DISABLE FUNCTION.
* FOR THE MULTIMODE HFBR-5207 TRANSCEIVER, PINS 5–9 ARE NOT USED.
,,,,,,
,,
,, ,
,,,,
,,
,
R3
C5
R4
TERMINATE AT
FIBER-OPTIC
TRANSCEIVER
INPUTS
Figure 4. Recommended Circuit Schematic.
clock recovery circuits. HP has
participated in several reference
design studies and is prepared to
share the findings of these studies
with interested customers. Con-
tact your local HP sales represen-
tative to arrange for this service.
Evaluation Circuit Boards
Evaluation circuit boards
implementing this recommended
circuit design are available from
Hewlett-Packard’s Application
Engineering staff. Contact your
local HP sales representative to
arrange for access to one if
needed.
Operation in -5.2 V Designs
For applications that require
-5.2 Vdc power supply level for
true ECL logic circuits, the
CDX2622 transceiver can be
operated with a V
CC
= 0 Vdc and
a V
EE
= -5.2 Vdc. This trans-
ceiver is not specified with an
operating, negative power supply
voltage. The potential compro-
mises that can occur with use of
-5.2 Vdc power are that the
absolute voltage states for V
OH
and V
OL
will be changed slightly
due to the 0.2 V difference in
supply levels. Also, noise
immunity may be compromised
for the CDX2622 transceiver
because the ground plane is now
the V
CC
supply point. The sug-
gested power supply filter circuit
shown in Figure 4 Recommended
Circuit Schematic should be
located in the V
EE
paths at the
transceiver supply pins. Direct
coupling of the differential data
and clock signals can be done
between the CDX2622 trans-
ceiver and the standard ECL
circuits. For guaranteed -5.2 Vdc
operation, contact your local
Hewlett- Packard Field Sales
Engineer for assistance.
A
∅E
B
C
∅F
D
TOP VIEW
DIM.
A
B
C
D
E
F
MILLIMETERS
MIN.
TYP.
20.32
33.02
2.54
2.54
1.8
0.7
2.0
0.9
0.071
0.027
MAX.
MIN.
INCHES
TYP.
0.8
1.3
0.1
0.1
0.079
0.035
MAX.
Figure 5. Recommended Board Layout Hole Pattern.
Recommended Solder Fluxes
and Cleaning/Degreasing
Chemicals
Solder fluxes used with the
CDX2622 fiber-optic transceiver
should be water-soluble, organic
solder fluxes. Some recom-
mended solder fluxes are Lonco
3355-11 from London Chemical
West, Inc. of Burbank, CA, and
100 Flux from Alpha- metals of
Jersey City, NJ.
Recommended cleaning and
degreasing chemicals for the
CDX2622 are alcohol’s (methyl,
isopropyl, isobutyl), aliphatics
(hexane, heptane) and other
chemicals, such as soap solution
or naphtha. Do not use partially
355
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