a
FEATURES
Programmable Sinusoidal Oscillator
Synthesized Synchronous Reference Output
Programmable Output Frequency Range: 2 kHz–20 kHz
“Loss-of-Signal” Indicator
20-Pin PLCC Package
Low Cost
APPLICATIONS
Excitation Source for:
Resolvers
Synchros
LVDTs
RVDTs
Pressure Transducers
Load Cells
AC Bridges
FBIAS
SEL1
SEL2
FREQUENCY
SELECT
Programmable
Oscillator
AD2S99
FUNCTIONAL BLOCK DIAGRAM
PUSH/
PULL
O/P STAGE
EXC
EXC
TO
TRANSDUCER
SINE WAVE
GENERATOR
SYNREF
SYNCHRONOUS
REFERENCE
LOS
AD2S99
PHASE
DETECT
LOGIC
SIN
COS
FROM
TRANSDUCER
GENERAL DESCRIPTION
The AD2S99 programmable sinusoidal oscillator provides sine
wave excitation for resolvers and a wide variety of ac transduc-
ers. The AD2S99 also provides a synchronous reference output
signal (3 V p-p square wave) that is phase locked to its SIN and
COS inputs. In an application, the SIN and COS inputs are
connected to the transducer’s secondary windings.
The synchronous reference output compensates for temperature
and cabling dependent phase shifts and eliminates the need for
external preset phase compensation circuits. The synchronous
reference output can be used as a zero crossing reference for
resolver-to-digital converters such as Analog Devices’ AD2S80A,
AD2S82A, AD2S83 and AD2S90.
The AD2S99 is packaged in a 20-pin PLCC and operates over
–40°C to +85°C.
PRODUCT HIGHLIGHTS
Dynamic Phase Compensation
The AD2S99 dynamically compensates for any phase variation
in a transducer by phase locking its synchronous reference out-
put to the transducer’s secondary windings.
Programmable Excitation Frequency
The excitation frequency is easily programmed to 2 kHz, 5 kHz,
10 kHz, or 20 kHz by using the frequency select pins. Interme-
diate frequencies are available by adding an external resistor.
Signal Loss Detection
The AD2S99 has the ability to detect if both the transducer sec-
ondary winding connections become disconnected from its SIN
and COS inputs. The “LOS” output pin pulls high when a sig-
nal loss is detected.
Integration
The AD2S99 integrates the transducer excitation, synchronous
reference, and loss of signal detection functions into a small,
cost effective package.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD2S99–SPECIFICATIONS
(V =
S
4.75 V to
Typ
2000
5000
10000
20000
5.25 V @ –40 C to +85 C unless otherwise noted)
Max
Units
Hz
Hz
Hz
Hz
±
10
±
20
±
5
±
10
%
%
%
%
%
%
%
%
V p-p/V
Test Conditions
SEL1
V
SS
V
SS
GND
GND
SEL2
V
SS
GND
V
SS
GND
Parameter
FREQUENCY OUTPUT RANGE
2 kHz
5 kHz
10 kHz
20 kHz
ACCURACY
Frequency
Min
AP Grade @ +25°C
AP Grade –40°C to +85°C
BP Grade @ +25°C
BP Grade –40°C to +85°C
AP Grade @ +25°C
AP Grade –40°C to +85°C
BP Grade @ +25°C
BP Grade –40°C to +85°C
Output Variation as Function of
Change in Power Supply Voltage
Amplitude
±
3
±
3
±
10
±
20
±
5
±
10
Power Supply Rejection Ratio
ANALOG OUTPUTS
Amplitude
EXC,
EXC
SYNREF
SYNREF OFFSET
Current Drive Capability
EXC,
EXC
V
S
=
±
5 V
Capacitive Drive
Total Harmonic Distortion
EXC,
EXC
ANALOG INPUTS SIN, COS
Amplitude
Phase Lock Range
Additional Phase Delay
1.8
–45
0.002
2
±
3
±
200
8
1000
V rms
V p-p
mV
mA rms
pF
dB
EXC to GND,
EXC
to GND
Square Wave
R
LOAD
= 500
Ω
EXC
to EXC
C
LOAD
= 1000 pF
–25
2.0
2.2
+45
±
10
±
10
V
SS
AGND
0.7
V
DD
0.5
+4.75
–4.75
0.6
0.8
+5.25
–5.25
±
15
+85
+150
V rms
Degrees
Degrees
Degrees
V dc
V dc
V dc
V rms
V dc
V dc
mA
°C
°C
I
OL
= 400
µA
50 kΩ Pull Up to V
DD
(Open
Drain Output)
AP Grade
BP Grade
FREQUENCY SELECT INPUTS
SEL1, SEL2
1
LOS OUTPUT
Output Low Voltage
Output High Voltage
SIN, COS LOS Threshold
POWER SUPPLIES
V
DD
V
SS
Quiescent Current I
DD
, I
SS
TEMPERATURE RANGE
Operating
Storage
±
8
No Load
–40
–65
NOTES
1
Frequency select pins SEL1 and SEL2 must be connected to appropriate voltage levels before power is applied.
Specifications subject to change without notice.
–2–
REV. B
AD2S99
ABSOLUTE MAXIMUM RATINGS*
PIN DESIGNATIONS
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V
Operating Temperature . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Analog Input Voltages (SIN and COS) . . . . . . . . . V
SS
– 0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to V
DD
+ 0.3 V
Frequency Select (SEL1, SEL2) . . . . . . . . . . . . . . V
SS
– 0.4 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to AGND + 0.4 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Pin
No.
1
2
3
5
6
1
7
10
11
12
16
1
17
18
19
2
20
2
Mnemonic
SEL2
SEL1
FBIAS
SIN
DGND
COS
SYNREF
LOS
V
DD
AGND
EXC
EXC
V
SS
V
SS
Description
Frequency Select 2
Frequency Select 1
External Frequency Adjust Pin
Resolver Output SIN
Digital Ground
Resolver Output COS
Synthesized Reference Output
Indicates When Both the SIN and
COS Are Below the Threshold.
Positive Power Supply
Analog Ground
Resolver Reference One
Resolver Reference Two
3
Negative Power Supply
Negative Power Supply
Power Supply Voltage (V
DD
to V
SS
) . . . . . .
±
4.75 V to
±
5.25 V
Analog Input Voltage (SIN and COS) . . . . . . . . 2 V rms
±
10%
Frequency Select (SEL1 and SEL2) . . . . . . . . . V
SS
to AGND
Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C
RECOMMENDED OPERATING CONDITIONS
ORDERING GUIDE
Model
AD2S99AP
AD2S99BP
*P = PLCC.
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Option*
P-20A
P-20A
NOTES
1
Pins 6 and 16 must be connected together.
2
Pins 19 and 20 must be connected together.
3
Resolver Reference two (EXC) is 180° phase advanced with respect to Resolver
Reference one (EXC).
PIN CONFIGURATION
FBIAS
SEL1
SEL2
3
NC
SIN
DGND
COS
NC
4
5
6
7
8
9
NC
2
1
20 19
18 EXC
V
SS
V
SS
AD2S99
TOP VIEW
(Not to Scale)
17 EXC
16 AGND
15 NC
14 NC
10 11 12 13
SYNREF
LOS
V
DD
NC
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD2S99 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
AD2S99
CONNECTING THE AD2S99 OSCILLATOR
20
18
16
FREQUENCY – kHz
Refer to Figure 1. Positive supply voltage V
DD
should be con-
nected to Pin 12 and negative supply voltage V
SS
should be con-
nected to both Pins 19 and 20.
Reversal of these power supplies will
destroy the device.
The appropriate voltage level for the power
supplies is
±
5 V dc
±
5%. Both V
SS
Pins (19 and 20) must be
connected together, and Digital Ground (Pin 6) must be con-
nected to Analog Ground (Pin 16) locally at the AD2S99.
V
SS
4.7µF
0.1µF
14
12
10
8
6
4
2
FBIAS
SEL1
SEL2
V
SS
V
SS
3
NC
SIN
DGND
COS
NC
4
5
6
7
8
9
2
1
20 19
18
17
EXC
EXC
AGND
RESOLVER
REF
SIN
0
0
4
8
12
16
20
24
ADDITIONAL RESISTANCE – kΩ
RESISTOR PULLUP TO V
DD
FROM FBIAS
28
AD2S99
16
Figure 2. Typical Added Resistance Value
COS
15 NC
14 NC
10
11 12 13
AD2S99 OSCILLATOR OUTPUT STAGE
NC
SYNREF
LOS
V
DD
NC
.
. R
*
.
X
100nF
TO AD2S80/
AD2S90 REF INPUT
100kΩ
The output of the AD2S99 oscillator consists of two sinusoidal
signals, EXC, and
EXC. EXC
is 180° phase advanced with re-
spect to EXC. The excitation winding of a transducer should be
connected across EXC (Pin 17) and
EXC
(Pin 18).
With low impedance transducers, it may be necessary to in-
crease the output current drive of the AD2S99. In such an in-
stance, an external buffer amplifier can be used to provide gain
(as needed), and additional current drive for the excitation out-
put (either EXC or
EXC)
of the AD2S99, providing a single
ended drive to the transducer. Refer to Figures 6, 7 and 8 for
sample buffer configurations.
The amplitude modulated SIN and COS output signals from a re-
solver should be connected as feedback signals to the AD2S99.
The SYNREF output compensates for any primary to secondary
phase errors in the resolver. These errors can degrade the accuracy
of a Resolver-to-Digital Converter (R/D Converter).
SIN, from the resolver, should be connected to the AD2S99 SIN
input and COS should be connected to the AD2S99 COS input.
The SIN Lo, COS Lo (resolver signal returns) should be con-
nected to AGND and the R/D Converter as applicable.
The synthesized reference (SYNREF) from the AD2S99 should
be connected to the reference input pin of the R/D Converter.
The SYNREF signal is a square wave at the oscillator frequency
of amplitude
±
3 V p-p and is phase coherent with the SIN and
COS inputs. If this signal is used to drive the reference input of
the AD2S90 R/D Converter, a coupling capacitor and resistor to
GND must be connected between the SYNREF output of the
AD2S99 and the REF input of the R/D Converter (see Figure
3). Please read the appropriate R/D Converter data sheets for
further clarification.
LOSS OF SIGNAL
50kΩ
V
DD
0.1µF
4.7µF
SEL2 = GND ]
–5kHz MODE
SEL1 = V
SS
]
INCREASE R
X
TO LOWER
OUTPUT FREQUENCY
(SEE GRAPH)
NC = NO CONNECT
*
R
X
IS ONLY REQUIRED FOR INTERMEDIATE FREQUENCIES.
FIXED FREQUENCIES ONLY REQUIRE A LINK.
Figure 1. Typical Configuration
It is recommended that decoupling capacitors are connected in
parallel between V
DD
and Analog Ground and V
SS
and Analog
Ground in close proximity to the AD2S99. The recommended
values for the decoupling capacitors are 100 nF (ceramic) and
4.7
µF
(tantalum). When multiple AD2S99s are used, separate
decoupling capacitors should be used for each AD2S99.
FREQUENCY ADJUSTMENT
The output frequency of the AD2S99 is programmable to four
standard frequencies (2, 5, 10, or 20 kHz) using the SEL1 and
SEL2 pins. The output can also be adjusted to provide interme-
diate frequencies by connecting a resistor from the FBIAS pin to
the positive supply V
DD
. The FBIAS pin is connected directly to
V
DD
during normal operation. A graph showing the typical
added resistance values for various intermediate frequencies is
provided in Figure 2. The procedure for obtaining an intermedi-
ate frequency is:
1. Set the output frequency via the SEL1, SEL2 pins to the fre-
quency immediately above the required intermediate frequency.
2. Connect the frequency adjust pin FBIAS to V
DD
via an exter-
nal resistor.
For example: to obtain an output frequency of 8 kHz, set the
nominal output frequency to 10 kHz by connecting SEL1 to
GND and SEL2 to V
SS
. Connect FBIAS to V
DD
via a 6 kΩ
resistor (refer to Figure 2).
During normal operation when both the SIN and COS signals
on the resolver secondary windings are connected to the
AD2S99, the LOS output pin of the AD2S99 (Pin 11) is at a
Logic Lo (<0.7 V). If both the SIN and COS signals on the re-
solver secondary windings fall below the LOS threshold level of
the AD2S99, the LOS pin of the AD2S99 will pull up to a
Logic Hi (V
DD
) level.
–4–
REV. B
AD2S99
AD2S99/AD2S90 TYPICAL CONFIGURATION
Figure 3 shows a typical circuit configuration for the AD2S99
Oscillator and the AD2S90 Resolver-to-Digital Converter. The
maximum level of the SIN and COS input signals to the
AD2S90 should be 2 V rms
±
10%. All the analog ground sig-
nals should be star connected to the AD2S90 AGND pin. If
shielded twisted pair cables are used for the resolver signals, the
shields should also be terminated at the AD2S90 AGND pin.
The SYNREF output of the AD2S99 should be connected to
the REF input pin of the AD2S90 via a 0.1
µF
capacitor with a
100 kΩ resistor to GND. This is to block out any dc offset in
the SYNREF signal. For more detailed information please refer
to the AD2S90 data sheet.
V
DD
0.1µF
FBIAS
SEL1
SEL2
V
SS
V
SS
V
SS
4.7µF
NC = NO CONNECT
NC 4
SIN
5
DGND
6
COS
7
NC 8
3
2
1
20 19
18
EXC
EXC
AGND
AD2S99
TOP VIEW
(Not to Scale)
17
16
SEL2 = GND
SEL1 = V
SS
F
OUT
= 5kHz
15 NC
14 NC
9 10 11 12 13
LOS
V
DD
NC
SYNREF
NC
50kΩ
V
DD
0.1µF
4.7µF
0.1µF
100kΩ
18 17 16 15 14
S4
19
20
S2
S2
R2
REF
R4
COS
S4
S3
SIN
S1
RESOLVER S1
4
POWER
RETURN
5
S3
1
2
3
REF
COS LO
COS
AGND
SIN
SIN LO
V
DD
V
DD
13
V
SS
12
DGND 11
V
DD
0.1µF
0.1µF
4.7µF
4.7µF
V
SS
AD2S90
TOP VIEW
(Not to Scale)
6
7
8
10
9
Figure 3. AD2S99 and AD2S90 Example Configuration
REV. B
–5–
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