BCM8501
PRODUCT
STS-192c/STM-64c
B C M 8 5 0 1
Brief
AND
O F
POS
FRAMER
S U M M A R Y
MAPPER
B E N E F I T S
F E AT U R E S
Packet over
•
Gbps) PHY SONET/SDH (POS) STS-192c (9.953
Generic, 16-bit microprocessor
•
control and register access interface for device
Standard IEEE 1149.1 Joint
•
test port for boundary scan Test Action Group (JTAG)
•
16-bit, 622.08 MHz, LVDS line interface
Serial
•
bytes interface for SONET/SDH transport overhead
•
16-bit General Purpose Input/Output (GPIO)
•
Low-power, 1.8/3.3V CMOS technology
•
612-pin HSBGA (Heat Sink Ball Grid Array) package
•
Industrial temperature range from -40°C to +85°C
Filters and
•
(APS) bytescaptures Automatic Protection Switch
(K1 K2).
Detects
•
crossingsignal degrade and signal failure threshold
alarms.
Captures
•
byte (S1). and debounces the synchronization status
Extracts and inserts
•
trace (J0), path tracethe 16-byte or 64-byte section
(J1) messages, and section/line
data communication channels (DCC).
CMOS-based device
•
economy of scale. uses the most effective silicon
Low power consumption
•
external cooling sources. eliminates the need for
•
Target applications:
• Multiprotocol switches
• Layer 3 switches
• Routers, packet switches, and hubs
Application Diagram
Link Layer Device
TFCLKP/N
TVAL_TCTRL
TDAT[63:0]
TFULL
TSOCP
TPRTY[3:0]
TERR
TEOP
TSIZE[2:0]
RFCLK_OUTP/N
RVAL_RCTRL
RDAT[63:0]
RFULL
RSOCP
RPRTY[3:0]
RERR
REOP
RSIZE[2:0]
BCM8501
TFCLKP/N
REFCLKP/N
TVAL_TCTRL
TPAR_DO[15:0]P/N
TDAT[63:0]
TPAR_CLKP/N
TFULL
LCKDET_CMU
TSOCP
TPRTY[3:0]
TERR
TEOP
TSIZE[2:0]
LOSN
RFCLK_OUTP/N
RVAL_RCTRL
RDAT[63:0]
RFULL
RSOCP
RPRTY[3:0]
RERR
REOP
RSIZE[2:0]
RPAR_DI[15:0]P/N
RPAR_CLKP/N
LOSB
LCKDET_CDR
BCM8110
622.08 MHz
Optical
Receiver
BCM8111
B C M 8 5 0 1
O V E R V I E W
Internal Block Diagram
TS_OVCLK
TS_TOH_DATA
TS_OVFP
TRST
TCK
TMS
TDI
TDO
TEST_CLK[6:1]
SCANEN
SCANMODE
Section/Line
DCC Insert
JTAG Test
Access Port
GPIO
TFCLKP/N
TVAL_TCTRL
TBUS[15:0]
TSDCLK
TSDCLK
TSD
TSD
Tx Section
O/H
Processor
REFCLKP/N
TPAR_DO[15:0]P/N
TPAR_CLKP/N
RPAR_DI[15:0]P/N
RPAR_CLKP/N
LCKDET_CMU
LCKDET_CDR
LOSB
Tx Line
O/H
Processor
Tx Path
O/H
Processor
Tx POS
Frame
Processor
TDAT[63:0]
TFULL
TSOCP
TPRTY[3:0]
TERR
TEOP
TSIZE[2:0]
RFCLK_OUTP/N
RVAL_RCTRL
RDAT[63:0]
RFULL
RSOCP
RPRTY[3:0]
RERR
REOP
RSIZE[2:0]
Parallel Line
Interface
Section
Trace
Buffer
Path
Trace
Buffer
Rx Section
O/H
Processor
Rx Line
O/H
Processor
Rx Path
O/H
Processor
Rx POS
Frame
Processor
Section/Line
DCC Extract
Alarm
Status
Microprocessor
Interfaces
RS_O VCLK
RS_TOH_DATA
RS_OVFP
The
BCM8501
User Network Interface is a monolithic
integrated circuit that implements SONET/SDH processing and
Packet over SONET mapping functions at the STS-192c/STM-
64-64c 9.953 Gbps rate. The
BCM8501
is configured,
controlled, and monitored through a generic 16-bit
microprocessor bus interface. The
BCM8501
also provides a
standard five-signal IEEE 1149.1 JTAG test port for boundary
scan board test purposes.
Broadcom
®
, the pulse logo
®
and
Connecting Everything
TM
are trademarks of
Broadcom Corporation and/or its subsidiaries in the United States and certain other countries.
All other trademarks are the property of their respective owners.
The
BCM8501
uses a low-power, +1.8V, 0.18µ CMOS
technology. It has LVTTL/CMOS-compatible digital
input/outputs. The CMOS I/O operates at 3.3V. The
BCM8501
is packaged in a 35 x 35 mm, 612-pin HSBGA package.
AD[15:0]
MA[7:0]
ALE
CS
RWB_WB
DSB_RB
RSTB
INTR
RSDCLK
RSD
RLDCLK
RLD
LOSN
RALRM
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2002 by BROADCOM CORPORATION. All rights reserved.
8501-PB02-R-3.4.02
SPI-4 Phase 1
System Interface
(HSTL)
Phone: 949-450-8700
FAX: 949-450-8710
Email: info@broadcom.com
Web: www.broadcom.com
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