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PRELIMINARY
RoboClock
®
CY7B9945V
High Speed Multi-phase PLL Clock Buffer
Features
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Functional Description
The CY7B9945V high speed multi-phase PLL clock buffer offers
user selectable control over system clock functions. This multiple
output clock driver provides the system integrator with functions
necessary to optimize the timing of high performance computer
and communication systems.
The device features a guaranteed maximum TTB window speci-
fying all occurrences of output clocks. This includes the input
reference clock across variations in output frequency, supply
voltage, operating temperature, input edge rate, and process.
Ten configurable outputs each drive terminated transmission
lines with impedances as low as 50Ω while delivering minimal
and specified output skews at LVTTL levels. The outputs are
arranged in two banks of four and six outputs. These banks
enable a divide function of 1 to 12, with phase adjustments in 625
ps–1300 ps increments up to ±10.4 ns. The dedicated feedback
output enables divide-by functionality from 1 to 12 and limited
phase adjustments. However, if needed, any one of the ten
outputs can be connected to the feedback input as well as driving
other inputs.
Selectable reference input is a fault tolerant feature that enables
smooth change over to a secondary clock source when the
primary clock source is not in operation. The reference inputs
and feedback inputs are configurable to accommodate both
LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
500 ps max Total Timing Budget (TTB™) window
24 MHz –200 MHz input and Output Operation
Low Output-output skew <200 ps
10 + 1 LVTTL Outputs driving 50Ω terminated lines
Dedicated feedback output
Phase adjustments in 625ps/1300 ps steps up to +10.4 ns
3.3V LVTTL/LVPECL, Fault Tolerant, and Hot Insertable
Reference Inputs
Multiply or Divide Ratios of 1 through 6, 8, 10, and 12
Individual Output Bank Disable
Output High Impedance Option for Testing Purposes
Integrated Phase Locked Loop (PLL) with Lock Indicator
Low Cycle-cycle jitter (<100 ps peak-peak)
3.3V Operation
Industrial Temperature Range: –40°C to +85°C
52-pin 1.4 mm TQFP package
Logic Block Diagram
FS
3
REFA+
REFA-
LO C K
REFB+
REFB-
REFSEL
FBK
MODE
FBF0
FBDS0
FBDS1
PLL
3
3
3
D iv id e
and
Phase
S e le c t
QF
1F0
1F1
1D S0
1D S1
1F2
1F3
3
3
3
3
3
3
D IS 1
1Q 0
1Q 1
D iv id e
and
Phase
S e le c t
1Q 2
1Q 3
2Q 0
2F0
2F1
2D S 0
2D S1
3
3
3
3
2Q 1
D iv id e
and
Phase
S e le c t
2Q 2
2Q 3
2Q 4
2Q 5
D IS 2
Cypress Semiconductor Corporation
Document Number: 38-07336 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised September 10, 2009
[+] Feedback
PRELIMINARY
RoboClock
®
CY7B9945V
Pinouts
Figure 1. Pin Configuration
REFA+
FBDS1
FBDS0
VCCQ
VCCN
VCCN
LOCK
GND
GND
FBK
1Q0
1Q1
QF
52 51 50 49 48 47 46 45 44 43 42 41 40
2F1
2F0
2DS1
G ND
2Q 0
VCCN
2Q 1
2Q 2
VCCN
2Q 3
G ND
1DS1
2DS0
1
39
2
38
3
37
4
36
5
35
6
34
7
33
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
REFA-
REFSEL
REFB-
REFB+
1F2
FS
G ND
1Q 2
VCCN
1Q 3
FBF0
1F0
VCCQ
CY7B9945V
DIS1
1DS0
GND
GND
VCCN
GND
Pin Definitions
Pin
34
40,39, 36,37
Name
FS
REFA+,
REFA-
REFB+,
REFB-
REFSEL
IO
Input
Input
Type
Description
Three level
Frequency Select.
This input must be set according to the nominal frequency
Input
(f
NOM
). See
Table 1.
LVTTL/
LVDIFF
Reference Inputs.
These inputs can operate as differential PECL or
single-ended TTL reference inputs to the PLL. When operating as a
single-ended LVTTL input, the complementary input is left open.
Reference Select Input.
The REFSEL input controls the configuration of
reference input When LOW, it uses the REFA pair as the reference input. When
HIGH, it uses the REFB pair as the reference input. This input has an internal
pull down.
Feedback Input Clock.
The PLL operates such that the rising edges of the
reference and feedback signals are aligned in phase and frequency. This pin
provides the clock output QF feedback to the phase detector.
38
Input
LVTTL
42
FBK
Input
LVTTL
28,18, 35,17, 2, 1 1F[0:3],
2F[0:1]
19,26
DIS[1:2]
Input
Input
Three level
Output Phase Function Select.
Each pair determines the phase of the
Input
respective bank of outputs. See
Table 3.
LVTTL
Output Disable.
Each input controls the state of the respective output bank.
When HIGH, the output bank is disabled to HOLD-OFF or High-Z state; the
disable state is determined by MODE. When LOW, outputs 1Q[0:3] and 2Q[0:5]
are enabled. See
Table 5.
14,12, 13,3
29
50,51
48,46, 32,30,
5,7,8,10, 20,22
44
[1:2]DS[0:
1]
FBF0
FBDS[0:1]
1Q[0:3],
2Q[0:5]
QF
Input
Input
Input
Output
Three level
Output Divider Function Select.
Each pair determines the divider ratio of the
Input
respective bank of outputs. See
Table 4.
Three level
Feedback Output Phase Function Select.
This input determines the phase
Input
of the QF output. See
Table 3.
Three level
Feedback Output Divider Function Select.
This input determines the divider
Input
ratio of the QF output. See
Table 4.
LVTTL
Clock Outputs with Adjustable Phases and f
NOM
Divide Ratios.
The output
frequencies and phases are determined by [1:2]DS[0:1], and 1F[0:3] and
2F[0:1], respectively. See
Table 3
and
Table 4.
Feedback Clock Output.
This output is connected to the FBK input. The output
frequency and phase are determined by FBDS[0:1] and FBF0, respectively.
See
Table 3
and
Table 4.
PLL Lock Indicator.
When HIGH, this output indicates that the internal PLL is
locked to the reference signal. When LOW, it indicates that the PLL is
attempting to acquire lock
Output
LVTTL
52
LOCK
Output
LVTTL
Document Number: 38-07336 Rev. *G
MODE
VCCQ
DIS2
1F3
1F1
2Q4
2Q5
Page 2 of 11
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PRELIMINARY
RoboClock
®
CY7B9945V
Pin Definitions
Pin
25
Name
MODE
IO
Input
Type
Description
Three level
This pin determines the clock outputs’ disable state.
When this input is
Input
HIGH, the clock outputs disables to high impedance state (High-Z). When this
input is LOW, the clock outputs disables to HOLD-OFF mode. When in MID,
the device enters factory test mode.
PWR
PWR
PWR
Power Supply for the Output Buffers
Power Supply for the Internal Circuitry
Device Ground
6,9,21, 31, 45, 47 VCCN
16,27, 41
4,11,15, 23,24,
33,43,49
VCCQ
GND
Block Diagram Description
The PLL adjusts the phase and the frequency of its output signal
to minimize the delay between the reference (REFA/B+,
REFA/B-) and the feedback (FB) input signals.
The CY7B9945V has a flexible REF input scheme. These inputs
enable the use of either differential LVPECL or single ended
LVTTL inputs. To configure as single ended LVTTL inputs, leave
the complementary pin open (internally pulled to 1.5V), then the
other input pin is used as a LVTTL input. The REF inputs are also
tolerant to hot insertion.
The REF inputs are changed dynamically. When changing from
one reference input to the other reference input of the same
frequency, the PLL is optimized to ensure that the clock outputs
period is not less than the calculated system budget (tMIN =
tREF (nominal reference period) – tCCJ (cycle-cycle jitter) –
tPDEV (max. period deviation)) while reacquiring lock.
The FS control pin setting determines the nominal operational
frequency range of the divide by one output (fNOM) of the
device. fNOM is directly related to the VCO frequency. The FS
setting for the device is shown in
Table 1.
For CY7B9945V, the
upper fNOM range extends from 96 MHz to 200 MHz.
Table 1. Frequency Range Select
FS
[1]
LOW
MID
HIGH
f
NOM
(MHz)
Min
24
48
96
Max
52
100
200
Divide and Phase Select Matrix
The Divide Select Matrix is comprised of three independent
banks: two of clock outputs and one for feedback. The Phase
Select Matrix, enables independent phase adjustments on
1Q[0:1], 1Q[2:3] and 2Q[0:5]. The frequency of 1Q[0:3] is
controlled by 1DS[0:1] while the frequency of 2Q[0:5] is
controlled by 2DS[0:1]. The phase of 1Q[0:1] is controlled by
1F[0:1], that of 1Q[2:3] is controlled by 1F[2:3] and that of 2Q[0:5]
is controlled by 2F[0:1].
The high fanout feedback output buffer (QF) connects to the
feedback input (FBK).This feedback output has one phase
function select input (FBF0) and two divider function selects
FBDS[0:1].
The phase capabilities that are chosen by the phase function
select pins are shown in
Table 3.
The divide capabilities for each
bank are shown in
Table 4.
Table 3. Output Phase Select
Control Signal
1F1
1F0
1F3
1F2
2F1
2F0
FBF0
LOW
LOW
LOW
MID
LOW
HIGH
MID
LOW
MID
MID
MID
HIGH
HIGH
LOW
HIGH
MID
HIGH
HIGH
Output Phase Function
1Q[0:1]
1Q[2:3]
2Q[0:5]
–4t
U
–3t
U
–2t
U
–1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
–4t
U
–3t
U
–2t
U
–1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
QF
–8t
U
–4t
U
–7t
U
N/A
–6t
U
N/A
[2]
N/A
BK1Q[0:1]
0t
U
0t
U
[2]
BK1Q[2:3]
N/A
+6t
U
N/A
+7t
U
N/A
+8t
U
+4t
U
Time Unit Definition
Selectable skew is in discrete increments of time unit (t
U
). The
value of a t
U
is determined by the FS setting and the maximum
nominal output frequency. The equation determines the t
U
value
as follows:
t
U
= 1/(f
NOM
*N).
N is a multiplication factor that is determined by the FS setting.
f
NOM
is nominal frequency of the device. N is defined in
Table 2.
Table 2. N Factor Determination
FS
LOW
MID
HIGH
N
32
16
8
CY7B9945V
f
NOM
(MHz) at which t
U
= 1.0 ns
31.25
62.5
125
Table 4. Output Divider Select
Control Signal
[1:2]DS1
[1:2]DS0
and FBDS1
and
FBDS0
LOW
LOW
LOW
MID
LOW
HIGH
Output Divider Function
Bank1
Bank2
Feedback
/1
/2
/3
/1
/2
/3
/1
/2
/3
Document Number: 38-07336 Rev. *G
Page 3 of 11
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PRELIMINARY
RoboClock
®
CY7B9945V
Table 4. Output Divider Select
Control Signal
[1:2]DS1
[1:2]DS0
and FBDS1
and
FBDS0
MID
LOW
MID
MID
MID
HIGH
HIGH
LOW
HIGH
MID
HIGH
HIGH
Output Divider Function
Bank1
Bank2
Feedback
/4
/5
/6
/8
/ 10
/ 12
/4
/5
/6
/8
/ 10
/ 12
/4
/5
/6
/8
/ 10
/ 12
Figure 2
shows the timing relationship of programmable skew
outputs. All times are measured with respect to REF with the
output used for feedback programmed with 0t
U
skew. The PLL
naturally aligns the rising edge of the FB input and REF input. If
the output used for feedback is programmed to another skew
position, then the whole t
U
matrix shifts with respect to REF. For
example, if the output used for feedback is programmed to shift
–4tU, then the whole matrix is shifted forward in time by 4tU.
Thus an output programmed with 4tU of skew gets effectively be
skewed 8t
U
with respect to REF.
Figure 2. Typical Outputs with FB Connected to a Zero-Skew Output
[3]
U
t
0
– 6t
U
t
0
– 5t
U
t
0
– 4t
U
t
0
– 3t
U
t
0
– 2t
U
t
0
– 8t
U
t
0
– 7t
U
t
0
– 1t
U
U
U
U
U
U
U
t
0
+7t
FBInput
REFInput
1F[1:0]
1F[3:2]
(N/A)
(N/A)
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
(N/A)
(N/A)
(N/A)
2F[1:0]
LL
LM
LH
(N/A)
(N/A)
(N/A)
(N/A)
MM
(N/A)
(N/A)
(N/A)
(N/A)
HL
HM
HH
–8t
U
–7t
U
–6t
U
–4t
U
–3t
U
–2t
U
–1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
+6t
U
+7t
U
+8t
U
Output Disable Description
The output of each output bank can be independently put into a
HOLD OFF or high impedance state. The combination of the
MODE and DIS[1:2] inputs determines the clock outputs’ state
for each bank. When the DIS[1:2] is LOW, the outputs of the
corresponding banks are enabled. When DIS[1:2] is HIGH, the
outputs for that bank are disabled to a high impedance (HI-Z) or
HOLD OFF state.
Table 5
defines the disabled outputs functions.
The HOLD OFF state is a power saving feature. An output bank
is disabled to the HOLD OFF state in a maximum of six output
clock cycles from the time the disable input is HIGH. When
disabled to the HOLD OFF state, outputs are driven to a logic
LOW state on their falling edges. This makes certain that the
output clocks are stopped without a glitch. When a bank of
Page 4 of 11
Document Number: 38-07336 Rev. *G
t
0
+8t
t
0
+1t
t
0
+2t
t
0
+3t
t
0
+4t
t
0
+5t
t
0
+6t
t
0
U
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